Staff Engineer - Packaging Layout Design & Simulation

JAC Recruitment Pte Ltd; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

A leading semiconductor back-end company seeks a Staff Engineer to design and develop semiconductor packaging layouts. Responsibilities include reviewing technical specifications, collaborating with cross-functional teams, and maintaining documentation. The ideal candidate will have experience with Cadence APD tools and a strong understanding of industry standards.

Qualifications

• Proven experience in semiconductor packaging layout design.
• Strong understanding of industry standards and design guidelines.
• Excellent collaboration and communication skills.

Responsibilities

• Design and develop semiconductor packaging layouts.
• Review technical specifications for compliance.
• Collaborate with cross-functional teams to ensure project execution.
• Maintain documentation according to procedures.
• Participate in process optimization and product development.

Skills

Collaboration

Communication

Technical specification interpretation

Tools

Cadence APD

Job description

Company and Job Overview

A leading semiconductor back-end company is looking for a Staff Engineer to be responsible for Packaging Layout Design and Simulation.

Responsibilities

Design and develop semiconductor packaging layouts in accordance with customer specifications and requirements.

Review technical specifications to ensure compliance with in-house and vendor design guidelines.

Perform layout designs, feasibility studies, and design modifications, verifying drawings against project inputs for accuracy and conformance to industry standards.

Collaborate effectively with customers, Technical Program Managers, Sales teams, Designers, and Assembly Engineers across different UTAC sites to ensure seamless project execution.

Travel as needed to support other UTAC locations or to conduct face-to-face meetings with customers.

Maintain comprehensive documentation and proper version control of all design outputs in compliance with UTAC procedures.

Participate actively in continuous improvement initiatives, including cost reduction, process optimization, and productivity enhancement related to package design.

Contribute to new product development and qualification, establishing robust processes suitable for mass production (MP).

Qualifications & Experience:

Proven experience in semiconductor packaging layout design, with specific expertise using Cadence APD tools.

Strong understanding of industry standards and design guidelines.

Ability to interpret and review technical specifications.

Excellent collaboration and communication skills to liaise with cross-functional teams and external clients.

Catherine Qu
JAC Recruitment Pte Ltd
EA Personnel: R22104823
EA Personnel Name: QU QIUSHI

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