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A recruitment firm specializing in technology placements is looking for a Verification Engineer in Singapore. The ideal candidate will have a Bachelor or Master's in Electrical/Electronics/Computer Engineering, with at least 1 year of experience in IC design verification using SystemVerilog and UVM. The role involves developing test plans, implementing a coverage matrix, and debugging tests for designs under test (DUT). Knowledge of HDL is essential.
Job Descriptions
Requirements
Ethos Search Associates Pte. Ltd.
EA Licence No: 13C6655
EA Reg No: R1109557 Rose