Snr Silicon Design Engineer

XILINX ASIA PACIFIC PTE. LTD.; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A global technology firm based in Singapore is looking for a dedicated individual to plan and execute physical designs for AMD's IP features. The role requires strong analytical and problem-solving skills, along with excellent communication abilities for collaboration across teams in different regions. Candidates should have a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering, and experience with various EDA tools and scripting languages. This is a unique opportunity to contribute to high-quality deliverables in a dynamic environment.

Qualifications

• Experience with IP level ASIC physical design including hierarchical implementation.
• Good understanding and hands‑on experience in timing constraints development.
• Experience automating workflows in a distributed computing environment.

Responsibilities

• Develop and implement plans for DFT and timing closure on complex digital circuits.
• Collaborate with design groups across disciplines to meet performance requirements.
• Maintain synthesis, DFT, and Static Timing Analysis scripts using best practices.
• Analyze and adjust scripts based on tool output to meet timelines.
• Communicate with project teams globally to resolve issues and meet goals.

Skills

Analytical skills

Problem-solving skills

Communication skills

Team player

Education

Bachelor's or Master's degree in Computer Engineering/Electrical Engineering

Tools

RTL2GDS EDA tools

Linux

Windows

Verilog

System Verilog

C

C++

Perl

Tcl

Makefile

Shell

Job description

THE ROLE:

The focus of this role is to plan, build, and execute the physical design of new and existing features for AMD’s IP, resulting in quality database for the final deliveries.

THE PERSON:

You have a passion for modern, complex physical design aspects of digital design. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Develop and implement plans to synthesize, implement Design-For-Test (DFT), and close timing on complex digital integrated circuits.
• Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
• Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule.
• Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements.

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC physical design including hierarchical implementation.
• Proficient in using physical design RTL2GDS EDA tools and working in Linux and Windows environments.
• Experienced with Verilog, System Verilog, C, and C++.
• Automating workflows in a distributed computing environment.
• Good understanding and hands‑on experience in timing constraints development.
• Scripting language experience: Perl, Tcl, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Computer Engineering/Electrical Engineering.

LOCATION:

Singapore