Senior/Staff Engineer STPG Product Engineering - Probe

1100 Micron SemiAsiaOP Pte Ltd; Singapore; On-site; SGD 70,000 - 90,000; Full time

Benefits offered by this job

Career growth opportunities

Exposure to advanced technology

Global collaboration

Job summary

1100 Micron SemiAsiaOP Pte Ltd in Singapore is looking for a Probe Product Engineer to own the probe strategy at wafer test. This role includes defining probe coverage, driving yield and quality outcomes, and collaborating across teams.

The ideal candidate should have a degree in Electrical/Electronics Engineering and possess strong skills in semiconductor devices and data-driven decision making. Opportunities for career growth within the product lifecycle are provided.

Qualifications

• Strong fundamentals in semiconductor devices and product engineering.
• Ability to use silicon data for effective decision-making.
• Interest in silicon learning and manufacturing integration.

Responsibilities

• Define and own probe coverage intent and objectives.
• Drive test efficiency improvements and yield learning.
• Support first-silicon bring-up and characterization.

Skills

Semiconductor devices

Analytical skills

Communication skills

Root-cause analysis

Education

Bachelor’s, Master’s, or PhD in Electrical / Electronics Engineering or related field

Job description

Job Description Summary

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM). This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements. The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.
• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.
• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.
• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.
• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.
• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.
• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.
• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.
• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.
• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.
• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.
• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.
• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.
• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.
• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI‑driven solutions and enabling data‑driven decision‑making across projects and teams.

Required Qualifications

• Bachelor’s, Master’s degree, or PhD in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.
• Strong fundamentals in semiconductor devices, wafer test, and product engineering.
• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.
• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.
• Strong analytical skills and ability to drive structured root‑cause analysis.
• Effective communication skills and ability to work across global, cross‑functional teams.

Career Growth & Impact

Direct ownership of probe strategy and quality outcomes across the product lifecycle. Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems. Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Equal Employment Opportunity Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail].