Senior/Engineer STPG Product Engineering - Probe

Micron Technology, Inc; Singapore; On-site; SGD 70,000 - 100,000; Full time

Benefits offered by this job

Choice of medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Job summary

Micron Technology, Inc in Singapore is seeking a Probe Product Engineer to own probe strategy and silicon learning at wafer test. This role involves collaborating with cross-functional teams to ensure robust probe solutions are aligned with product requirements and driving yield, quality, and cost optimization.

Candidates with a Bachelor's, Master's, or PhD in Electrical or Electronics Engineering, coupled with strong semiconductor knowledge and analytical skills, are encouraged to apply. The position offers compelling career growth within the engineering lifecycle.

Qualifications

• Strong fundamentals in semiconductor devices and product engineering.
• Demonstrated ability to analyze silicon behavior and drive yield decisions.
• Effective communication across global teams.

Responsibilities

• Define and sustain probe coverage strategy.
• Support first-silicon bring-up and device characterization.
• Drive test efficiency improvements and manage cost optimization.

Skills

Semiconductor knowledge

Analytical skills

Cross-functional collaboration

Education

Bachelor’s/Master’s/PhD in Electrical/Electronics Engineering or related field

Job description

Job Description Summary

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Career Growth & Impact

• Direct ownership of probe strategy and quality outcomes across the product lifecycle.
• Exposure to advanced technology nodes, customer‑driven requirements, and large‑scale manufacturing systems.
• Clear growth paths across senior technical contributor, product leadership, or people management tracks within STPG Product Engineering.

Key Responsibilities

Probe Coverage Strategy & Ownership

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.
• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.
• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.
• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.
• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.
• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.
• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.
• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.
• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.
• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.
• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.
• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.
• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.
• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.
• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.
• Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

• Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data‑driven decision‑making across projects and teams.

Required Qualifications

• Bachelor’s, Master’s degree, or PhD in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.
• Strong fundamentals in semiconductor devices, wafer test, and product engineering.
• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.
• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.
• Strong analytical skills and ability to drive structured root‑cause analysis.
• Effective communication skills and ability to work across global, cross‑functional teams.

Job Profile(s)

• Product Development Engineer 4

Relocation level: TBD

Benefits

We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

Equal Employment Opportunity

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.