Senior Probe Strategy Engineer: Silicon Learn & Yield

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE. LTD.; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE. LTD. in Singapore seeks a Probe Product Engineer within STPG Product Engineering to own probe strategy and silicon learning across pre‑silicon to HVM, aligning with Design, DFT, DV, and Reliability teams.

You will define probe coverage, limits, and guard‑bands based on silicon data, drive yield and test‑cost outcomes, and support NPI with manufacturability risk mitigation.

Qualifications

• Bachelor's, Master's degree, or PhD in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.
• Strong fundamentals in semiconductor devices, wafer test, and product engineering.
• Demonstrated ability to use silicon behavior and characterization data to make informed probe, yield, and coverage decisions.
• Experience or strong interest in silicon learning, device behavior, yield mechanisms, DFT intent, or design‑to‑manufacturing integration.
• Strong analytical skills and ability to drive

Responsibilities

• Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.
• Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.
• Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.
• Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.
• Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.
• Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.
• Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.
• Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).
• Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.
• Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.
• Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.
• Provide early silicon learning to accelerate probe flow stabilization and yield ramp.
• Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.
• Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.
• Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.
• Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.
• Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.
• Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.
• Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.
• Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

Education

Bachelor's/Master's/PhD in Electrical / Electronics Engineering or related semiconductor field

Job description

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE. LTD. in Singapore seeks a Probe Product Engineer within STPG Product Engineering to own probe strategy and silicon learning across pre‑silicon to HVM, aligning with Design, DFT, DV, and Reliability teams.

You will define probe coverage, limits, and guard‑bands based on silicon data, drive yield and test‑cost outcomes, and support NPI with manufacturability risk mitigation.