Senior Memory Verification Engineer

Broadcom; Northwest; On-site; SGD 60,000 - 100,000; Full time

Job summary

Join a forward-thinking company as a Foundation IP Senior Memory Verification Engineer, where you will be part of an elite team responsible for the verification of cutting-edge AI products. This role involves performing functional verification, conducting signal integrity analyses, and developing automation scripts to streamline processes. You will collaborate closely with design leads and managers to ensure the highest quality in memory validation. If you are passionate about tackling complex challenges and eager to contribute to innovative technologies, this opportunity is perfect for you.

Qualifications

• 5 years of experience in memory verification and transistor level simulations.
• Strong understanding of signal integrity and EM/IR analysis.

Responsibilities

• Perform functional verification and resolve design discrepancies.
• Conduct signal integrity analysis and propose solutions.
• Develop scripts to automate verification flow.

Skills

Transistor level circuit behavior

Signal integrity analysis

EM/IR analysis

Automation scripting

Memory behavioral models

DFT schemes

Communication skills

Problem-solving

Education

Bachelor's in Electrical Engineering

Tools

Simulation tools

Job description

Job Description:

Foundation IP Senior Memory Verification Engineer

We are looking for energetic and passionate design engineers to join our Central Engineering Group and be part of an elite team responsible for the verification of foundation IP for AI products including memory compilers and custom macros of all types on the bleeding edge of process technology. We have multiple positions at all experience levels.

Available Job Responsibilities

• Perform functional verification, root cause and resolve design discrepancies
• Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them
• Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them
• Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins
• Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them
• Perform various QA and validation checks to ensure accurate timing and power models
• Develop scripts to automate verification flow and data analysis
• Support silicon debugs and correlation to spice models
• Coordinate with memory design leads, modeling leads, and managers to define and execute on the memory validation plan
  
  
  

Preferred Skills

• Good understanding of transistor level circuit behavior
• Good understanding of signal integrity, EM/IR, and reliability analysis
• Proficiency in running simulators, writing automation scripts, and are tools savvy
• Good understanding of memory behavioral and physical models
• Understanding of DFT schemes and chip level integration is a plus
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking
• Passion for solving complex problems and willingness to learn
  
  
  

Qualifications

Requires a BS in Electrical or Computer Engineering and 5 years of related experience