Senior Design Verification Engineer

Charterhouse Pte Ltd; Singapore; On-site; USD 80,000 - 120,000; Full time

Job summary

An innovative firm is seeking a Design Verification Engineer to join their dynamic verification team. In this role, you will leverage cutting-edge methodologies to tackle complex design challenges and drive innovation in verification practices. You'll be responsible for developing robust verification environments using UVM, C/C++, and formal verification techniques, all while striving for zero-defect results. This is an excellent opportunity for experienced professionals or recent graduates with a passion for excellence and collaboration. If you're ready to push the boundaries of technology and contribute to a high-performing team, this position is perfect for you.

Qualifications

• 8+ years of experience in design verification or exceptional academic results as a recent graduate.
• Expertise in UVM and strong collaboration skills are essential.

Responsibilities

• Develop and deploy verification strategies for complex designs.
• Collaborate with engineers to ensure defect-free designs.

Skills

UVM verification methodology

C/C++ programming

system emulation

formal verification

collaboration

quality-driven mindset

Education

MSEE/BSEE in Electrical Engineering

MSEE/BSEE in Computer Engineering

Tools

mixed-mode simulation

Job description

About the Job:

Join our client's passionate and dynamic verification team where we constantly push the boundaries of technology. As a Design Verification Engineer, you will be working with cutting-edge verification methodologies to tackle ever-increasing design complexities. You'll be involved in developing and deploying state-of-the-art solutions using techniques like UVM, C/C++ co-simulation, system emulation, mixed-mode simulation, and formal verification. Their goal is clear: zero-defect results with the most innovative approach to a broad verification space.

Key Responsibilities:

• Work with a talented team on verification projects using advanced methodologies.
• Develop and deploy verification strategies across a wide range of design complexities.
• Collaborate with engineers to achieve defect-free designs.
• Utilize UVM, C/C++, system emulation, and formal verification techniques.
• Drive innovation in verification practices for improved efficiency and results.

Requirements:

• MSEE/BSEE in Electrical Engineering or Computer Engineering.
• 8+ years of experience: Bring your wealth of experience to the table, or if you’re a recent graduate with exceptional academic results, we’re excited to mentor you into an amazing career.
• Expertise in UVM verification methodology: You’ll bring your knowledge of UVM to develop robust and scalable verification environments that challenge traditional limits.
• Quality-driven mindset: You have an unwavering commitment to excellence, always striving for the best results while ensuring the highest standards of quality and precision.
• Strong collaborator: You thrive in a team environment, valuing open communication and working with others to solve complex problems and drive innovation.
• Bonus points: Experience in video processing and video analytics? Fantastic! A passion for general programming? Even better! We value diverse skills and interests that complement your verification expertise.

If you're eager to push the envelope in design verification and ready to contribute to a team striving for zero-defects, we want to hear from you!