Senior Design Engineer - PNR/STA

Broadcom; Northwest; On-site; SGD 60,000 - 100,000; Full time

Job summary

An established industry player is seeking a dynamic Senior Design Engineer specializing in Place and Route and STA. This role involves developing automation flows for complex digital systems and collaborating with cross-functional teams to ensure timing closure. The ideal candidate will bring extensive experience with advanced PNR tools and scripting skills, contributing to innovative projects in cutting-edge technology. Join a forward-thinking company where your expertise will drive impactful solutions and enhance technological advancements. If you are passionate about engineering and eager to tackle complex challenges, this opportunity is perfect for you.

Qualifications

• 6+ years of experience in Place and Route/STA development.
• Hands-on experience with ICC2, Innovus, and scripting in TCL/PERL.

Responsibilities

• Develop automation flows for complex digital/mixed signal blocks.
• Define constraints for complex blocks to achieve timing closure.

Skills

Synthesis

ICC2

Fusion Compiler

Innovus

Prime Time

TCL

PERL

Automation

Signal and Power Floor Plan

ECO Implementation

Education

B.S Degree

M.S Degree

Tools

ICC2

Innovus

Prime Time

Star-RC

Tweaker

Job description

Job Description:

Senior Design Engineer: Place and Route (PNR), STA(Static Timing Analysis)

Broadcom Central Engineering Group is looking for energetic and passionate Place and Route/STA Engineer. The Successful candidate will be responsible to work in one or more domains of Place and Route, STA development for complex Digital IP subsystems, Semi-custom macros across all types of bleeding edge process technologies.

Available Job Responsibilities

1. Netlist to GDS2 automation flow development for complex digital/mixed signal blocks using PNR tools like ICC2 or Innovus in advanced technology nodes.
2. Define the Floor Plan/placement/routing/Timing constraints in ICC for Complex blocks including BIST to achieve correct by construct DRC/LVS and timing closure.
3. Interact with the Cross functional team (Synthesis/STA/DNE) to close the loop in timing violations/DRC/LVS.
4. Constraints automation to achieve predictable timing closure through automation with minimal ECOs.
5. Perform PNR Architectural feasibilities with multiple power islands with Optimum Utilization, EM, IR.
6. Develop Fully Automated PNR, STA development flow to close timing to meet broader frequency requirements.

Skill Sets

1. Hands on Experience with Synthesis, ICC2, Fusion compiler, Innovus, Prime time tools.
2. Hands on experience in defining ICC2/Synthesis constraints that meets timing closure needs.
3. In-depth knowledge of Signal and Power Floor plan with minimal EM/IR violations.
4. In-depth expertise with all ICC2/STA options to handle de-ratings, Options to reduce cross talk.
5. Familiarity with ECO implementation, Familiarity with Tools like Tweaker.
6. Hands on expertise with TCL/PERL to automate the end to end PNR/STA flow.
7. Experience to handle a complex Netlist with multiple frequency domains and ICC timing closure.
8. Hands on experience in analyzing and correlating STA .vs. ICC timing reports.
9. Complete exposure to Synopsys Timing closure tools; Star-RC, Prime time, PTSI. Exposure to cadence timing closure flow is a big plus.
10. Strong Automation and scripting skills using Perl/Python to analyze timing/noise reports and drive for swift timing closure.

Additional Traits

1. Strong team player with ability to work across multiple geographies.
2. Strong Technical and Behavioral competency with a Can do attitude in driving complex projects.

Qualification

1. B.S Degree with minimum of 6+ Years’ experience in the relevant domain.
2. M.S Degree with minimum of 4+ Years’ experience in the relevant domain.