Senior Backend PD Engineer - Chip Floorplan & Tape-out

AMLOGIC SINGAPORE PRIVATE LIMITED; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

AMLOGIC SINGAPORE PRIVATE LIMITED is seeking an experienced Physical Design engineer to lead Place & Route activities for advanced process nodes. You will collaborate with front-end design teams to implement chip floorplan, clock architecture, and power plans, and you will handle backend/PD tasks from Netlist to GDSII, including P&R, formal verification, STA, and tape-out.

The ideal candidate has a bachelors degree in ECE/CS and at least five years of PD experience, strong communication,

Qualifications

• Bachelor's degree in electronic engineering, microelectronics, or computer science.
• At least five years of Place & Route experience; hands-on in advanced technology required.
• Strong communication, confidence and self-motivation.

Responsibilities

• Work with the front-end design team to complete the chip floorplan, clock architecture, and power plan.
• Responsible for backend/PD tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tape-out.
• Research the physical design methodology of advanced process nodes, and build an automatic physical design platform.

Skills

Place & Route experience

Education

Bachelor's degree or above

Job description

AMLOGIC SINGAPORE PRIVATE LIMITED is seeking an experienced Physical Design engineer to lead Place & Route activities for advanced process nodes. You will collaborate with front-end design teams to implement chip floorplan, clock architecture, and power plans, and you will handle backend/PD tasks from Netlist to GDSII, including P&R, formal verification, STA, and tape-out.

The ideal candidate has a bachelors degree in ECE/CS and at least five years of PD experience, strong communication,