RTL Design Engineer (ASIC/SOC)

HKM HR MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

Une entreprise innovante recherche un Ingénieur Senior en Conception RTL pour diriger le développement et la validation de produits ASIC/SoC. Le candidat idéal possédera un Master en Ingénierie Électrique avec 5 ans d'expérience en conception numérique. Le poste implique de collaborer avec des équipes transversales tout en mentorant des ingénieurs juniors, le tout dans un environnement dynamique et stimulant.

Qualifications

• Minimum 5 ans d'expérience en RTL/SoC/digital design.
• Compétences en Verilog et SystemVerilog requises.
• Familiarité avec les protocoles AMBA APB et AXI.

Responsibilities

• Diriger la conception, simulation et validation RTL pour les produits de l'entreprise.
• Intégrer et valider les blocs IP pour garantir la fonctionnalité du système.
• Collaborer avec les équipes pour le codage RTL et la préparation à la fabrication.

Skills

RTL/SoC/digital design

Verilog

SystemVerilog

pre-layout simulation

post-layout simulation

Education

Master in Electrical Engineering

Tools

VCS

Verdi

Job description

Responsibilities:

• Lead RTL design, simulation, and verification for company ASIC/SoC products, ensuring robustness.
• Integrate and validate IP blocks for seamless system functionality.
• Analyze requirements for Power, Performance, and Area (PPA), optimizing design trade-offs.
• Collaborate with backend team in RTL coding, implementation, and synthesis for successful tapeout.
• Create and maintain reusable IPs for AI/in-memory computing.
• Support Post-Si testing to ensure product functionality and quality.
• Mentor junior engineers to facilitate their professional growth.
• Contribute to design reviews for improved product performance and reliability.
• Stay current on RTL design methodologies for efficiency and quality.
• Collaborate with cross-functional teams for successful product development.

Requirements:

• Minimum Master in Electrical Engineering with 5 years of working experience with emphasis on RTL/SoC/digital design.
• Proficient in Verilog and SystemVerilog.
• Proficient in VCS, Verdi, or similar industry-standard tools.
• Skilled in pre-layout and post-layout simulation.
• Knowledgeable about the design flow and collaboration with backend teams.
• Familiar with AMBA APB and AXI protocols.
• Familiar with RISC/Arm or other core architectures.

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HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [e-mail] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628