R & D Engineer – PVD/Plating

STATS CHIPPAC MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

A leading semiconductor company in Singapore seeks a PVD/Plating Engineer to lead projects related to PVD/Plating processes. The role involves developing process capability, conducting risk assessments, and ensuring project documentation. Candidates must have a relevant engineering degree and experience in semiconductor assembly.

Qualifications

• At least 2 years working experience in semiconductor assembly line.
• Knowledge in PVD/Plating process: machine, materials, procedures, operations, quality requirements.
• This role requires travel to Korea for a minimum of 2 months for training.

Responsibilities

• Lead assigned projects.
• Develop PVD/Plating process capability and establish process stability.
• Perform Technical Risk Assessments involving the PVD/Plating Process.

Skills

Project planning

Technical Writing Skills

Knowledge in PVD/Plating process

Knowledge in DOE and Statistical Tools

Education

Degree in Engineering (Mechanical/Chemical Engineering or Chemistry/Physics)

Job description

Key Job Accountabilities:

• Lead assigned projects.
• To develop PVD/Plating process capability and establish process stability for high volume manifesting.
• Perform PVD/Plating DOE for the characterization and optimization PVD/Plating process required for the qualification New Technologies or New Products.
• Understanding in metal to metal, metal to organic material adhesion and compatibility.
• Understanding in copper plating chemistry.
• Perform PVD/Plating capabilities reviews for New Technologies or New Products requirements.
• Perform Technical Risk Assessments involving the PVD/Plating Process of NP/EP/NT/ET being developed and qualified.
• Support engineering samples and qualification builds related to PVD/Plating.
• Prepare, review, and update the documentations related to PVD/Plating projects.
• Trains Operations and transfer the developed and qualified technologies.
• Support Operations during LVM for excursion free ramp up.

Required Experience and Qualifications:

• Degree in Engineering (Mechanical/Chemical Engineering or science in Chemistry/Physic)
• Good project planning, monitoring and control skills.
• Knowledge in PVD/Platingprocess: machine, materials, procedures, operations, quality requirements
• Knowledge in DOE and Statistical Tools such as JMP
• Good Technical Writing Skills.
• This role requires to travel to Korea for a min of 2 month for training.
• At least 2 years working experience in semiconductor assembly line.