PVD Process Engineer (R&D)

STATS CHIPPAC MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

Une entreprise de gestion des semi-conducteurs à Singapour recherche un ingénieur spécialisé en développement de processus PVD. Ce poste implique le développement et l'optimisation des équipements PVD, avec une forte interaction entre les équipes de fabrication pour améliorer les performances des matériaux. Les candidats doivent avoir un diplôme pertinent et au moins 3 ans d'expérience dans le secteur, avec des compétences solides en gestion de projet et en leadership.

Qualifications

• Au moins 3 ans d'expérience pratique dans des fabs semi-conducteurs, axé sur le développement de processus PVD.
• Bonne compréhension du dépôt de matériaux pour les nœuds logiques.
• Expérience avérée en qualification de processus et transfert de technologie.

Responsibilities

• Développer et optimiser les processus PVD pour les métaux d'interconnexion.
• Collaborer avec des équipes pour mettre en œuvre de nouveaux matériaux et capacités.
• Installer et optimiser les équipements PVD pour la production.

Skills

Project Management

Problem Solving

Cross-functional Leadership

Education

Bachelor’s or Master’s in Materials Science, Chemical Engineering, Electrical Engineering, or Physics

Tools

PVD Tools (AMAT, ULVAC, LAM)

Job description

Key Job Accountabilities

• Develop and optimize PVD processes for interconnect metals and barrier layers in alignment with technology roadmap
• Evaluate and introduce new PVD tools and hardware platforms in collaboration with leading equipment vendors
• Propose tailored PVD solutions based on customer product and integration requirements
• Install and optimize PVD equipment for production and development use
• Support technology transfer and process ramp-up in new fab locations (e.g., Singapore)
• Collaborate with integration, yield, equipment, and process module teams to implement new materials and capabilities
• Apply deep fab-level process knowledge, particularly in BEOL/FEOL metallization and advanced logic node integration
• Directly impacts advanced packaging reliability and electrical performance through development of PVD interconnect and barrier/liner layers
• Influences equipment selection, material integration, and yield improvement in high-volume production
• Key contributor to fab startups and technology enablement in global manufacturing sites

Required Experience and Qualifications:

• Bachelor’s or Master’s degree in Materials Science, Chemical Engineering, Electrical Engineering, Physics, or related field
• At least 3 years of hands-on experience in semiconductor fabs, with focus on PVD process development
• Strong understanding of deposition of Ti, TiW, NiV, Au, Cu and barrier/liner materials for logic nodes
• Practical experience with PVD tools (AMAT, ULVAC, LAM) including recipe tuning and hardware optimization
• Proven track record in process qualification, technology transfer, and yield improvement
• Strong project management, problem-solving, and cross-functional leadership skills
• Experience in metallization for Bumping and MEOL in advanced packaging
• Excellent communication and leadership skills for team alignment and mentoring
• Experience in process development for 2.5D/3D, TSV, CoWoS, or fan-out packaging technologies (Preferred)
• Hands-on experience operating PVD equipment (Preferred)
• Proven capability in cross-process integration and optimization (Preferred)
• Familiarity with reliability evaluation and qualification criteria (Preferred)
• Proficiency in technical documentation/reporting and English communication with global customers (Preferred)