Principal Analog Mixed-Signal IC Layout Engineer

Borr Drilling; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading company in innovative connectivity solutions is seeking an Analog Mixed-Signal IC Layout Engineer to join their talented team. You will be responsible for developing high-speed analog IC layouts, focusing on advanced node CMOS technologies. Ideal candidates will have substantial experience in layout extraction and analysis, ensuring circuit quality while adhering to industry DRC standards.

Qualifications

• 5+ years of experience in layout for high-speed analog IC designs.
• Proficient in layout extraction tools and analysis of layout parasitics.
• Strong understanding of EMIR and antenna DRC rules.

Responsibilities

• Design sophisticated advanced node CMOS products through layout.
• Minimize parasitic and skew, with matching and EMIR considerations.
• Collaborate with design engineers across multiple time zones.

Skills

Layout extraction

High-speed analog IC design

EMIR DRC rules

TCL scripting

Education

Bachelor or advanced Diploma in Electrical Engineering

Job description

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description:As an Analog Mixed-Signal IC Layout Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include floor planning, creating layout of building blocks and integrating layout for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, antenna rule on top of DRC and LVS. The company seeks a highly motivated and team orientated individual to work with both layout and design engineers across multiple time zoneBasic Qualifications:

• Bachelor or advanced Diploma degree in EE

Required Experience:

• 5+ years of experience developing layout for highspeed analog IC designs in finFET technology
• Experience with layout extraction tools and to analyze layout parasitic to achieve high quality layout for highspeed circuits
• EMIR and antenna DRC rules aware layout practices
• Experience writing SKILL and TCL scripts is highly recommended

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.