Principal Analog Mixed-Signal IC Layout Engineer

Astera Labs; Singapore; On-site; USD 80,000 - 140,000; Full time

Job summary

Join a forward-thinking company as a Principal Analog Mixed-Signal IC Layout Engineer, where you will play a crucial role in designing advanced node CMOS products. This position involves floor planning and creating layouts for complex circuits such as PLLs, ADCs, and amplifiers, while focusing on minimizing parasitics and ensuring compliance with DRC and LVS standards. The company values diversity and innovation, encouraging applicants from all backgrounds to contribute their unique perspectives. This is an exciting opportunity to be part of a team that is at the forefront of technology, shaping the future of connectivity solutions.

Qualifications

• 5+ years in high-speed analog IC layout development.
• Proficient in EMIR and antenna DRC rules.

Responsibilities

• Design advanced node CMOS products and integrate layouts for various circuits.
• Collaborate with design engineers across multiple time zones.

Skills

Layout for high-speed analog IC designs

FinFET technology

EMIR and antenna DRC rules

SKILL scripting

TCL scripting

Education

Bachelor's degree in Electrical Engineering

Advanced Diploma in Electrical Engineering

Tools

Layout extraction tools

Job description

Principal Analog Mixed-Signal IC Layout Engineer

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Description:

As an Analog Mixed-Signal IC Layout Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include floor planning, creating layout of building blocks and integrating layout for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, antenna rule on top of DRC and LVS. The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones.

Basic Qualifications:

Bachelor or advanced Diploma degree in EE.

Required Experience:

1. 5+ years of experience developing layout for high-speed analog IC designs in finFET technology.
2. Experience with layout extraction tools and to analyze layout parasitic to achieve high quality layout for high-speed circuits.
3. EMIR and antenna DRC rules aware layout practices.
4. Experience writing SKILL and TCL scripts is highly recommended.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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