Physical Chip Design Engineer

SUNLUNE (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

A semiconductor design company is looking for a skilled Physical Chip Design Engineer in Singapore. The ideal candidate will lead low-power and high-performance chip design processes, managing full-chip physical design workflows. Candidates should have a Bachelor’s degree in Electronics or related fields, and 4-5 years of experience in physical design with expertise in 12nm technologies. Proficiency in tools like Synopsys IC Compiler and Cadence Innovus is required.

Qualifications

• 4-5 years of hands-on experience in physical design.
• Experience in low-power, high-performance chip design.
• Expertise in 12nm and below semiconductor technologies.

Responsibilities

• Lead and optimize low-power physical design workflows.
• Oversee full-chip floor planning and place-and-route.
• Design and optimize power distribution networks.
• Resolve timing challenges and ensure power integrity.
• Conduct thorough physical verification processes.

Skills

Low-power design

Full-chip floor planning

Place-and-route methodologies

Physical verification

Power network design

Scripting (Perl, TCL, Python, C++)

Education

Bachelor’s degree in Electronics, Electrical Engineering, or Computer Science

Tools

Synopsys IC Compiler

Cadence Innovus

Static Timing Analysis (STA) tools

Job description

Overview

We are looking for a highly skilled Physical Chip Design Engineer to lead the development of low-power and high-performance chip design processes. This is a critical role that requires deep expertise in advanced semiconductor technologies and the ability to drive full-chip physical design workflows from start to finish.

Responsibilities

• Low-Power Physical Design Workflows: Lead and optimize processes to enhance energy efficiency while maintaining chip performance.
• Full-Chip Floor Planning & Place-and-Route: Oversee floor planning to ensure optimal performance, power, and area. Manage place-and-route processes for efficient, functional designs.
• Power Network Design & Analysis: Design and optimize power distribution networks, perform grid analysis to ensure power integrity and low-power design.
• Timing Closure, Power Integrity, & Signal Integrity: Resolve timing challenges, ensure power and signal integrity signoff, and perform necessary optimizations.
• Physical Verification (DRC & LVS): Conduct thorough physical verification, including Design Rule Checks (DRC) and Layout Versus Schematic (LVS) to ensure compliance with design specifications.

Qualifications

• Education: Bachelor’s degree or higher in Electronics, Electrical Engineering, Computer Science, or related field. Advanced degrees (Master’s/Ph.D.) are a plus.
• Experience: 4-5 years of hands-on experience in physical design, with expertise in low-power, high-performance chip design. Experience with 12nm and below semiconductor technologies and tape-out processes is essential.
• Technical Skills:
  • Expertise in full-chip floor planning, place-and-route methodologies, and physical verification (including DRC and LVS).
  • In-depth knowledge of power network design, IR drop analysis, and timing closure.
  • Proficiency in Synopsys IC Compiler, Cadence Innovus, or similar tools.
  • Proficiency with Static Timing Analysis (STA) tools.
• Programming Skills: Strong scripting skills in Perl, TCL, Python, and C++.