NAND PI Design Rule Snr Engineer

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Micron Technology, Inc. in Singapore seeks an experienced engineer to own design rule release, DRC waivers, mask definitions, and related specifications for R&D and production designs.

You will collaborate with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design, and Quality & Reliability to drive milestones, ensure DRC quality, and support yield and process improvements across next-gen NAND devices.

Qualifications

• Master's Degree with at least 5 years of experience in semiconductor industry in Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development
• Exposure to design & layout, ability to do minor layout and experience with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE is highly desired
• Understanding of Advanced NAND process flow, as well as the function and purpose of major NAND components, such as BL sensing, Word-line driver, CMOS under array, etc.
• Familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle

Responsibilities

• Responsible for Design rule release, Design Rule check waivers, Mask and related DRC definitions, Mask review and sign off, Process Requirement Specifications, etc. for R&D and Production Designs
• Drive/Contribute to deliver key milestones starting from Project Kick Off till End of Life
• Collaborate with a network of stakeholders including Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design and Quality & Reliability to help direct development efforts for a new Advanced NAND generation
• Ensure the quality of DRCs (Design Rule Checks) released with appropriate reaction to deviation from established design rules and proper documentation
• Work with Yield Enhancement, Product Engineers, Defect analysis, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design
• Help design and evaluate test structures to provide data for next generation devices and to quantify process margin on current devices
• Summarize complex problems, derive, and explain actions taken to address them
• Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment
• Define sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and timelines
• Ensure the best possible communication between NAND Design Rule and other key stakeholders
• Enthusiastically identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniques
• Assure timely documentation and feedback of R&D activities regarding design rule improvements to production parts still in design phase.

Education

Master's Degree in relevant field

Bachelor's Degree in relevant field

Tools

Cadence Virtuoso

K2view

Mentor Graphics DRV/RVE

Job description

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

Main Responsibilities

• Responsible for Design rule release, Design Rule check waivers, Mask and related DRC definitions, Mask review and sign off, Process Requirement Specifications, etc. for R&D and Production Designs

• Drive/Contribute to deliver key milestones starting from Project Kick Off till End of Life

• Collaborate with a network of stakeholders including Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design and Quality & Reliability to help direct development efforts for a new Advanced NAND generation

• Ensure the quality of DRCs (Design Rule Checks) released with appropriate reaction to deviation from established design rules and proper documentation

• Work with Yield Enhancement, Product Engineers, Defect analysis, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design

• Help design and evaluate test structures to provide data for next generation devices and to quantify process margin on current devices

• Summarize complex problems, derive, and explain actions taken to address them

• Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment

• Define sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and timelines

• Ensure the best possible communication between NAND Design Rule and other key stakeholders

• Enthusiastically identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniques

• Assure timely documentation and feedback of R&D activities regarding design rule improvements to production parts still in design phase.

Requirements

• Master's Degree with at least 5 years of experience or, Bachelor's Degree with at least 8 years of experience in semiconductor industry in the areas Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development

• Exposure to design & layout, ability to do minor layout and experience with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE is highly desired

• Understanding of Advanced NAND process flow, as well as the function and purpose of major NAND components, such as BL sensing, Word-line driver, CMOS under array, etc.

• Familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich lifefor all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.