LPU Chip Architect: Dataflow AI Inference Expert

Canaan Inc.; Singapore; On-site; SGD 120,000 - 190,000; Full time

Job summary

Canaan Inc. seeks a senior AI chip architect to lead LPU architecture, including static dataflow computing arrays and on-chip SRAM hierarchy.

You will collaborate with the compiler team to align hardware microarchitecture and drive hardware-software co-design, ensuring efficient inference performance. Responsibilities include performance benchmarking against GPU/NPU baselines, MoE/multimodal model tracking, FPGA prototype verification, and coordinating tape-out with back-end teams.

Qualifications

• Master’s degree or above in Microelectronics, IC, or Computer Architecture with 2+ years in AI chip design.
• Familiar with static dataflow and systolic architectures; knowledge of Prefill/Decode inference helpful.

Responsibilities

• Lead architecture definition of LPU chips with static dataflow and SRAM hierarchy.
• Collaborate with compiler team to define hardware microarchitecture and co-design.
• Model power, bandwidth and latency; benchmark against GPU/NPU architectures.
• Track MoE and multimodal model inferences; iterate architecture for next-gen inference.
• Participate in chip front-end design, FPGA prototype verification, and tape-out with back-end teams.
• Research dataflow chip architectures of overseas benchmarks and deliver competitive analyses.

Skills

AI chip architecture

Hardware-software co-design

Systolic array architecture

Static dataflow architecture

Performance benchmarking

Large model inference

Education

Master’s degree or above in Microelectronics/Integrated Circuit/Computer Architecture

Tools

Chip front-end design flow

Groq architecture familiarity

Job description

Canaan Inc. seeks a senior AI chip architect to lead LPU architecture, including static dataflow computing arrays and on-chip SRAM hierarchy.

You will collaborate with the compiler team to align hardware microarchitecture and drive hardware-software co-design, ensuring efficient inference performance. Responsibilities include performance benchmarking against GPU/NPU baselines, MoE/multimodal model tracking, FPGA prototype verification, and coordinating tape-out with back-end teams.