Low-Latency FPGA Developer for Trading Platforms (Singapore)

United States Digital Space LLC; Singapore; On-site; SGD 120,000 - 200,000; Full time

Benefits offered by this job

Medical insurance

Gym membership

Breakfast and lunch provided

Casual dress code

Job summary

United States Digital Space LLC is seeking an experienced FPGA Developer to join a high-frequency prop trading environment. The role focuses on architecting low-latency connections to global exchanges, building Ethernet-based stacks, and delivering efficient hardware-software interfaces.

Ideal candidates have 5–10 years of FPGA experience, proficiency in Verilog/SystemVerilog, C/C++, and a solid grasp of network protocols (Ethernet, PCIe) along with FPGA design flows.

Qualifications

• Bachelor's degree in Electrical Engineering
• 5-10 years of FPGA development experience
• Verilog or SystemVerilog programming
• C or C++ programming
• Experience with Ethernet protocols, PCIe, and/or switching and routing in network equipment
• FPGA design flow including synthesis, place & route, static timing analysis
• Strong understanding of network PHY interfacing

Responsibilities

• Architect low-latency connections to global financial exchanges in collaboration with software teams
• Build Ethernet-based communication stacks directly from FPGA to user space software
• Integrate network stacks to connect to various exchanges
• Develop and optimize interfaces between FPGA hardware and software components
• Document specifications clearly and communicate effectively in a fast-paced environment

Job description

United States Digital Space LLC is seeking an experienced FPGA Developer to join a high-frequency prop trading environment. The role focuses on architecting low-latency connections to global exchanges, building Ethernet-based stacks, and delivering efficient hardware-software interfaces.

Ideal candidates have 5–10 years of FPGA experience, proficiency in Verilog/SystemVerilog, C/C++, and a solid grasp of network protocols (Ethernet, PCIe) along with FPGA design flows.