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A leading technology company based in Singapore is seeking an experienced Analog Layout Designer. You will be responsible for advanced node processes and critical block designs, requiring deep knowledge of CMOS/Bi-CMOS/SOI/FinFET processes. The ideal candidate should excel in problem-solving, routing congestion, and ensure the robustness of designs through collaboration with verification and process engineering teams.
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Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL
Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL
Floor Planning, Parasitic Extraction, Timing Closure, Physical Verification, DFM, PrimeTime, Tcl Scripting, Perl Scripting,Power Planning, Place , Route, Clock Planning, Analog IP Integration, Signal Integrity Analysis, DFY, Tapeout, Crosstalk Delay Analysis, Noise Glitch Analysis, Electrical Rules Analysis, Variations Analysis, Modeling Techniques, Synopsys ICC2
Transmitters, Receivers, Equalization, System Simulation, Layout Design, Physical Design, Physical Verification, Parasitic Extraction, Verilog,CMOS Analog, Mixed Signal Circuit Design, Transistor Level Design, Gigabit Circuits, Circuit Simulation, Full Chip Verification, Scripting Skills, Verilog AMS
Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL
Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL
Floor Planning, Parasitic Extraction, Timing Closure, Physical Verification, DFM, PrimeTime, Tcl Scripting, Perl Scripting,Power Planning, Place , Route, Clock Planning, Analog IP Integration, Signal Integrity Analysis, DFY, Tapeout, Crosstalk Delay Analysis, Noise Glitch Analysis, Electrical Rules Analysis, Variations Analysis, Modeling Techniques, Synopsys ICC2
Transmitters, Receivers, Equalization, System Simulation, Layout Design, Physical Design, Physical Verification, Parasitic Extraction, Verilog,CMOS Analog, Mixed Signal Circuit Design, Transistor Level Design, Gigabit Circuits, Circuit Simulation, Full Chip Verification, Scripting Skills, Verilog AMS