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Layout Specialist

ACL Digital

Singapore

On-site

SGD 70,000 - 90,000

Full time

7 days ago
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Job summary

A leading technology company based in Singapore is seeking an experienced Analog Layout Designer. You will be responsible for advanced node processes and critical block designs, requiring deep knowledge of CMOS/Bi-CMOS/SOI/FinFET processes. The ideal candidate should excel in problem-solving, routing congestion, and ensure the robustness of designs through collaboration with verification and process engineering teams.

Qualifications

  • Excellent work experience in Analog Layout design in advanced node processes.
  • Strong grasp of Analog Layout concepts, including Matching and Electromigration.
  • Experience in layout parasitic extraction and working with simulation teams.

Responsibilities

  • Conduct layout parasitic extraction and validate design performance.
  • Work closely with the verification team to address layout-related issues.
  • Follow design rules, guidelines, and best practices for manufacturability.

Skills

Analog Layout design
Routing Congestion
Physical Verification
Hands-on experience in critical blocks
Problem-solving skills

Education

Degree in Electrical Engineering or related field

Tools

Cadence
Mentor EDA tools

Job description

    You should have excellent work experience in Analog Layout design in advanced node processes. Hands-on experience in critical blocks such as BGR, LDO, Charge pump, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Current Mirrors, Comparator, Differential Amplifier, etc. is required. Your understanding of CMOS / Bi-CMOS / SOI / FinFET process should be outstanding. You must possess a strong grasp of Analog Layout concepts, including Matching, Electromigration, Latch-up, Coupling, Cross-talk, IR-drop, Active and Passive parasitic devices, etc.Your problem-solving skills should be top-notch, especially in Routing Congestion and Physical Verification in Custom Layout. It will be essential for you to work closely with the verification team to address layout-related issues and ensure design robustness. Following design rules, guidelines, and best practices is crucial to ensure design manufacturability and yield.Collaboration with process engineers to understand process requirements and optimize layout designs accordingly is expected. You will be responsible for conducting layout parasitic extraction and working with the simulation team to validate and optimize design performance. Your participation in design reviews and contribution to overall design improvements is highly valued.It is important for you to stay updated with the latest advancements in analog layout techniques, process technologies, and industry standards.,
  • Job Tags routing, it network, layout design
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Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL

Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL

Floor Planning, Parasitic Extraction, Timing Closure, Physical Verification, DFM, PrimeTime, Tcl Scripting, Perl Scripting,Power Planning, Place , Route, Clock Planning, Analog IP Integration, Signal Integrity Analysis, DFY, Tapeout, Crosstalk Delay Analysis, Noise Glitch Analysis, Electrical Rules Analysis, Variations Analysis, Modeling Techniques, Synopsys ICC2

Transmitters, Receivers, Equalization, System Simulation, Layout Design, Physical Design, Physical Verification, Parasitic Extraction, Verilog,CMOS Analog, Mixed Signal Circuit Design, Transistor Level Design, Gigabit Circuits, Circuit Simulation, Full Chip Verification, Scripting Skills, Verilog AMS

Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL

Routing, Timing Closure, SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, CMOS, BiCMOS, SOI, Physical Verification, DRC, LVS, ERC, Antenna, DFM, Leadership skills, Communication skills,Mixed Signal Layout design, FinFET processes, PNR flow, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, AMS IP integration, Routing Congestion, Custom Layout, LPE, Analog layout techniques, Circuit principles, Cadence, Mentor EDA tools, VirtuosoXL

Floor Planning, Parasitic Extraction, Timing Closure, Physical Verification, DFM, PrimeTime, Tcl Scripting, Perl Scripting,Power Planning, Place , Route, Clock Planning, Analog IP Integration, Signal Integrity Analysis, DFY, Tapeout, Crosstalk Delay Analysis, Noise Glitch Analysis, Electrical Rules Analysis, Variations Analysis, Modeling Techniques, Synopsys ICC2

Transmitters, Receivers, Equalization, System Simulation, Layout Design, Physical Design, Physical Verification, Parasitic Extraction, Verilog,CMOS Analog, Mixed Signal Circuit Design, Transistor Level Design, Gigabit Circuits, Circuit Simulation, Full Chip Verification, Scripting Skills, Verilog AMS

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