Layout Engineer

Borr Drilling; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

A leading company in the drilling industry is seeking an experienced Layout Engineer. The ideal candidate will have strong layout knowledge, with proficiency in Cadence Layout tools and a Bachelor's in Electronics Engineering. This role involves quality assurance for layouts and mentoring junior engineers while adapting to new methodologies.

Qualifications

• Minimum 3-4 years experience in layout design preferred.
• Fresh graduates may be considered.
• Strong knowledge in submicron & Finfet processes (16nm to 3nm).

Responsibilities

• Understand and apply layout guidelines and technical requirements.
• Complete quality layout and verification within schedule.
• Lead team in new technology design rules.

Skills

Layout knowledge

Chip integration

ESD understanding

Script Programming

Teamwork

Education

Bachelor's in Electronics Engineering

Tools

Cadence Layout tools VIRTUOSO

CALIBRE verification tools

Job description

Job Description:

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O), new process rules and other technical requirements for quality layout.

Schedule time-line & layout floor-planning

Complete quality layout and verification within planned schedule (without supervision for experienced engineer)

Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team

Skill Set / Requirements:

Strong layout knowledge with a minimum of 3 to 4 years of experience is preferred. Fresh Bachelor Electronics engineering graduates or less than 3 years of layout experience may be considered.

Extensive experience in full custom and/or analog layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration (EMIR) in CMOS process.

Good experience in Floor-planning, hierarchy layout and chip integration.

Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools.

Good understanding of Latch-up and ESD in CMOS process and implementation for IO layout design.

Knowledge of Script Programming and SKILL Programming would be a plus.

Self-reliant, with ability to work independently as well as a team.

Strong layout knowledge in submicron & Finfet process, e.g. 16nm, 7nm, 5nm, 3nm

Additional Skill sets for Layout leads:

Review and lead team on new technology design rules, compile documentation of layout methodology, layout flow and guidelines.

Good leadership quality on project management to lead and train a team of junior layout engineers