Layout Engineer

Broadcom Inc.; Northwest; On-site; SGD 80,000 - 100,000; Full time

Job summary

An established industry player is seeking a skilled layout engineer to join their dynamic team. This role involves applying layout guidelines and technical requirements to ensure high-quality designs. With a focus on full custom and analog layout design, you will leverage your expertise in Cadence Layout tools and physical verifications to deliver exceptional results. You will also have the opportunity to lead and mentor junior engineers, fostering a collaborative environment while driving innovation in layout methodologies. If you are passionate about cutting-edge technology and eager to make a significant impact, this position is for you.

Qualifications

• 3-4 years of layout experience preferred; fresh graduates may be considered.
• Strong knowledge in submicron & Finfet processes required.

Responsibilities

• Ensure quality layout and verification within planned schedules.
• Lead team on new technology design rules and methodology documentation.

Skills

Layout Design

Analog Design

Physical Verification

Floor-planning

Chip Integration

Script Programming

SKILL Programming

Team Collaboration

Education

Bachelor in Electronics Engineering

Tools

Cadence Layout tools VIRTUOSO

CALIBRE Verification tools

Job description

Job Description:

Responsible to understand and apply all necessary layout guidelines (standard cells, I/O memories), new process rules and other technical requirements for quality layout.

Schedule time-line & layout floor-planning.

Complete quality layout and verification within planned schedule (without supervision for experienced engineer).

Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team.

Skill Set / Requirements:

Strong layout knowledge with a minimum of 3 to 4 years of experience is preferred. Fresh Bachelor Electronics engineering graduates or less than 3 years of layout experience may be considered.

Extensive experience in full custom and/or analog layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration (EMIR) in CMOS process.

Good experience in Floor-planning, hierarchy layout and chip integration.

Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools.

Good understanding of Latch-up and ESD in CMOS process and implementation for IO layout design.

Knowledge of Script Programming and SKILL Programming would be a plus.

Self-reliant, with ability to work independently as well as a team.

Strong layout knowledge in submicron & Finfet process, e.g. 16nm, 7nm, 5nm, 3nm.

Additional Skill sets for Layout leads:

Review and lead team on new technology design rules, compile documentation of layout methodology, layout flow and guidelines.

Good leadership quality on project management to lead and train a team of junior layout engineers.