Junior AI Chip DFT Engineer

SUNLUNE (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 40,000 - 60,000; Full time

Job summary

A technology company in Singapore is looking for a motivated Junior AI Chip DFT Engineer. The role involves assisting in the design and testing of AI chip architectures, performing simulations, and supporting yield improvement. Ideal candidates should have a Bachelor's degree in a relevant field and some understanding of DFT methodologies. Strong problem-solving skills and attention to detail are essential for success in this position.

Qualifications

• Bachelor's degree is essential for this role.
• Basic understanding of DFT methodologies is required.
• Familiarity with simulations is advantageous.

Responsibilities

• Assist in design and implementation of DFT architecture.
• Participate in functional verification and simulations.
• Support yield improvement and fault analysis activities.

Skills

Basic understanding of DFT methodologies

Familiarity with functional verification

Basic understanding of yield improvement concepts

Strong problem-solving skills

Attention to detail

Willingness to learn

Education

Bachelor’s degree in Electronics Engineering, Computer Science, or a related field

Tools

Scripting languages (e.g., TCL, Perl, Python)

Job description

Job Overview

We are seeking a motivated and detail-oriented Junior AI Chip DFT (Design for Test) Engineer to contribute to the testability of our innovative AI chip designs. This role will involve learning and assisting in the implementation of DFT architectures, integrating test circuits (Scan, Mbit, Memory repair, Bscan), performing simulations, and supporting test vector development and yield improvement efforts under the guidance of senior engineers.

Key Responsibilities

• Assist in the design and implementation of DFT architecture at the chip level, focusing on learning and applying testing circuits such as Scan, Mbit, Memory repair, and Bscan.
• Learn to implement DFT circuits and integrate them into the chip, understanding timing constraints for DFT mode convergence.
• Participate in functional verification, pre-simulation, post-simulation, and power simulation of DFT circuits. Assist in troubleshooting and resolving issues.
• Contribute to the development of high-coverage, low-cost test vectors and learn to validate them through simulation and timing analysis.
• Support yield improvement and fault analysis activities. Assist with testing SDC constraint files in testing modes and contribute to timing and power convergence in the backend.

Qualifications

• Bachelor’s degree in Electronics Engineering, Computer Science, or a related field.
• Basic understanding of DFT methodologies, including Scan, Mbit, Memory repair, and Bscan.
• Familiarity with functional verification and simulations (pre/post, power simulation) is a plus.
• Exposure to developing test vectors and performing timing analysis is beneficial.
• Basic understanding of yield improvement and fault analysis concepts.
• Familiarity with scripting languages (e.g., TCL, Perl, Python) is a plus.
• Strong problem-solving skills, attention to detail, and a willingness to learn and collaborate.