IO/ESD Custom Layout Engineer

PERSOL SINGAPORE PTE. LTD.; Singapore; On-site; SGD 60,000 - 80,000; Full time

Job summary

PERSOL SINGAPORE PTE. LTD. is seeking a Custom Layout Engineer to join its engineering team in Singapore. You will be responsible for physical design implementation across various process platforms including Foundation IP, Analog IP, and RFIC.

Applicants should possess a Bachelor’s degree in Electrical/Electronic Engineering along with a minimum of 3 years of relevant experience. Knowledge of advanced CMOS technologies and proficiency in layout tools are essential for ensuring high-quality delivery in projects.

Qualifications

• Minimum of 3 years of experience in custom Foundation IP (IO/ESD) and/or RF/Analog layout.
• Hands-on experience in advanced CMOS technologies (FinFETs/GAA) essential.
• Strong knowledge of design for manufacturability (DFM) and SI/PI.

Responsibilities

• Implement physical layout for Foundation IP, Analog IP, and RFIC across processes.
• Manage complete layout process including floorplanning and QA sign-off.
• Communicate effectively with multi-functional teams for optimized layout.

Skills

Custom Foundation IP layout implementation

RF/Analog layout design

Floorplanning techniques

Cadence/Synopsys tools

Physical verification

Education

Bachelor’s degree in Electrical/Electronic Engineering

Tools

Cadence layout editor

Synopsys tools

Job description

Overview

We are seeking result-driven candidates who can excel in a fast-pace work environment and possess a strong desire to make a meaningful impact within the organization. You will be part of the Custom Layout engineering team in undertaking physical design implementation of Foundation IP, Analog IP and RFIC for next-generation process platform developments.

Job Responsibilities

• Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including IO/ESD Foundation IP, Analog IP and RFIC, across multiple process nodes and diversified foundries.
• Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning layout construction, physical verification and QA flow sign-off.
• Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
• Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area.

Requirements

• Bachelor’s degree in Electrical/Electronic Engineering.
• Minimum of 3 years of direct experience in custom Foundation IP (IO/ESD) and/or RF/Analog layout implementation. Hands-on experience in advanced CMOS technologies (FinFETs/GAA) in a critical factor.
• Proficient in technical knowledges related to: Foundry DRM of advanced CMOS technologies, design for manufacturability (DFM), floorplanning techniques for hierarchical layout designs, SI/PI, EM/IR and ESD backend implementation flows.
• Strong knowledge in floor-planning techniques at different hierarchies, with emphasis on power mesh planning, critical block placement, critical signal routing, matching and top-down integration flow.
• Proficient in Cadence/Synopsys layout editor and physical verification tools; analytical and skillful in debugging physical verification such as DRC/LVS/ERC/ANT/PERC and all other verifications.
• Effective cross-team communication and time management skills.
• Proficient in IO/ESD layout and familiar with the layout requirement is a plus.

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