Integrated Circuit Designer

MARVELL ASIA PTE LTD; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

A leading company specializing in integrated circuit solutions seeks a Master's degree holder in Electrical/Computer Engineering for a role focused on developing support for advanced logic design and timing analysis. The ideal candidate will have a strong foundation in digital logic, scripting skills, and experience with EDA tools, contributing to both design and timing improvements in an international work environment.

Qualifications

• Master’s in Electrical/Computer Engineering or related majors.
• Experience in creating and testing logic blocks.
• Solid knowledge of timing analysis and synthesis concepts.

Responsibilities

• Develop and support block-level and partition-level construction flows.
• Perform synthesis, PnR, and timing analysis on complex logic blocks.
• Interact with RTL design team to resolve design modifications.

Skills

Scripting skills (Perl, Tcl, Python)

Timing analysis

Circuit design

Knowledge of Verilog/VHDL

Education

Master in Electrical Engineering

Master in Computer Engineering

Job description

• Develop and support Marvell's block-level and partition-level construction and signoff flows, incorporating industry standard EDA tools
• Perform synthesis, PnR, timing analysis, and backend checks on complex logic blocks
• Develop and implement timing and logic ECOs
• Interact with the RTL design team to drive design modifications to resolve congestion and timing issues
• Work with the global timing team in debugging/resolving any block-level timing issues seen at full chip
• Interact with tool vendors to drive tool improvements and perform tool evaluations of new tools/functions
• Design and develop the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams.

Requirements:

• Master in Electrical Engineering/Computer Engineering, or related majors with emphasis on digital logic course and projects that involved circuit design, testing, and timing analysis.
• Have work or course experience where you created and tested a logic block, then were able to look at the quality of results to ID improvements.
• Solid knowledge of formulas for timing analysis and concepts for synthesis and place and route.
• Strong scripting skills in languages such as Perl, tcl, or Python
• Knowledge of Verilog/VHDL