[IC Design] ASIC RTL Design Engineer - High-Speed Interfaces

Ambition Singapore; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

A leading company is seeking an experienced ASIC RTL Design Engineer to work on high-speed memory interfaces in Singapore. This role requires developing RTL code and collaborating closely with verification and software teams. Strong familiarity with ASIC development processes and at least 6 years of experience in the field is essential for this position. The successful candidate will have a Bachelor's or Master's degree in relevant engineering fields and a proven track record in ASIC design.

Benefits

SGD1,000 referral bonus

SGD350 shopping vouchers for referrals

Qualifications

• Minimum 6 years of ASIC design experience for staff engineer level; 10+ years for senior staff engineer.
• Strong familiarity with ASIC development processes.
• Familiarity with high-speed interface protocols such as DDR, SerDes, and PCIe preferred.

Responsibilities

• Develop RTL code for high-speed memory interfaces.
• Perform LINT checking and sanity testing to ensure robust design implementation.
• Collaborate with verification teams for lab debugging and validation.

Skills

Verilog HDL coding

Problem-solving

Collaboration

Education

Bachelor's degree in Communications, Electronic Engineering, Computer Engineering

Master's degree

Tools

EDA tools

Job description

We are seeking an experienced ASIC RTL Design Engineer to join our team working on high-speed memory interfaces. This role involves developing RTL code, collaborating closely with verification and software teams, and supporting debugging and system performance tuning for advanced semiconductor products.

Participate in defining high-level product specifications, microarchitecture, and implementation of high-speed memory interfaces.

Perform RTL coding, LINT checking, and sanity testing to ensure robust design implementation.

Collaborate with verification teams to support lab debugging and validation activities.

Work with software teams and customers to troubleshoot, debug, and optimize system-level performance.

Bachelor's degree in Communications, Electronic Engineering, Computer Engineering, or related field; Master's degree preferred.

Minimum 6 years of ASIC design experience for staff engineer level; 10+ years for senior staff engineer, with strong familiarity with ASIC development processes.

Proficient in Verilog HDL coding and experienced with EDA tools for synthesis and timing analysis.

Familiarity with high-speed interface protocols such as DDR, SerDes, and PCIe is preferred.

Strong problem-solving skills with a customer-oriented approach and ability to deliver timely solutions.

Excellent organizational and communication skills, with ability to collaborate effectively across teams.

If this job isn't quite right for you, but you know someone who would be great at this role, why not take advantage of our referral scheme? We offer SGD1,000 or SGD350 in shopping vouchers for every referred candidate who we place in a role. Terms & Conditions Apply. https://www.ambition.com.sg/refer-a-friend