End-to-End SoC Design Engineer – Tape-out Ready

RICORE TECHNOLOGY PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

RICORE TECHNOLOGY PTE. LTD. is seeking a skilled SoC architect to collaborate across cross-functional teams on high-performance chip design. The role covers front-end RTL, clock/reset, NoC development, and integration with synthesis.

The candidate will evaluate PPA, support design verification, and contribute to back-end silicon bring-up and ramp-up activities. A strong track record in tape-out and experience with ARM or RISC‑V cores is preferred.

Qualifications

• End-to-end SoC design experience with tape-out track record.
• High-performance, high-bandwidth chip experience on advanced nodes preferred.
• Proficient with CHI, AXI3/4/5, AHB, APB and ACE.
• Hands-on PPA design/optimization for SoC design & verification (RISC-V or ARM).
• Experience with Lint, CDC, and Synthesis tool flows.

Responsibilities

• Participate in architecture design and define high-performance specifications.
• Front-end chip design: RTL, clock/reset, low-power, NoC, integration and synthesis.
• Conduct PPA evaluation and optimisation for modules/subsystems.
• Support DV team on module/system verification activities.
• Engage in chip back-end iterations: performance and power analysis.
• Participate in verification, post-layout simulation, silicon bring-up and ramp-up.

Skills

SoC design

RTL design

Clock & reset design

Low-power design

NoC development

SoC integration & synthesis

Education

Bachelor's degree in Electronic Engineering or related field

Tools

Lint

CDC

Synthesis

Job description

RICORE TECHNOLOGY PTE. LTD. is seeking a skilled SoC architect to collaborate across cross-functional teams on high-performance chip design. The role covers front-end RTL, clock/reset, NoC development, and integration with synthesis.

The candidate will evaluate PPA, support design verification, and contribute to back-end silicon bring-up and ramp-up activities. A strong track record in tape-out and experience with ARM or RISC‑V cores is preferred.