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An innovative research program seeks a Senior/Postdoctoral Associate to advance semiconductor wafer technology. This role involves hands-on cleanroom tasks, wafer characterization, and collaboration with an interdisciplinary team. You will be at the forefront of pioneering research, working with cutting-edge optoelectronic devices and semiconductor processes. Join a dynamic environment where your expertise will directly impact industrial applications and contribute to groundbreaking advancements in photonic technology. If you are passionate about materials science and engineering, this opportunity is perfect for you.
Wafer-Scale Integrated Sensing Devices based on Optoelectronic Metasurfaces (WISDOM) focuses on semiconductor wafer growth and processing for photonic applications.
This program aims to pioneer a wafer-scale integrated platform which seamlessly combines metasurface optics, optoelectronic devices with a focus on light emitting diodes (LEDs) and vertical surface emitting laser arrays (VCSELs), and silicon complementary metal-oxide semiconductor (CMOS) electronics.
Researchers from MIT, NUS, NTU, A*STAR, Stanford University and University of Illinois form a uniquely qualified interdisciplinary team possessing the skills and infrastructure needed to perform the proposed research. WISDOM program will also involve a strong network of industry partners which are committed to development and translation of the WISDOM technology, thereby enabling outcomes from the program to make a direct impact on industrial applications.
The WISDOM IRG at SMART is seeking a qualified candidate for a Senior/Postdoctoral Associate position jointly supervised by Prof. Chuan Seng Tan and Prof. Juejun Hu. This position will entail the following technical responsibilities:
1. Perform cleanroom processing tasks including (but not limited to): photolithography, deposition of dielectric thin films, grinding and polishing of wafers, wafer bonding, thermal processing of wafers, wafer cleaning with wet chemistry.
2. Carry out characterization of wafers, including: microscope inspection, wafer bow measurement, surface morphology, electron microscopy, photo/electroluminescence, and working with external measurement service provider.
3. Coordinate and interface with external foundries on wafer-scale integration and advanced packaging process development.
4. Work with a team to fulfil wafer production planning and output, and lead the continual improvement project for wafer-level integration.
5. Perform other duties as assigned.
1. Ph.D. Degree in Materials Science, Mechanical Engineering, Electronic/Electrical Engineering, or any related discipline.
2. Prior experience in the semiconductor area (e.g. working in cleanrooms, handling semiconductor wafers/components etc.) is helpful, and experience operating cleanroom tools is preferred.
3. Prior experience in semiconductor foundry tape-out is preferred.
4. Experience in die/wafer advanced packaging is a plus and will be considered favourably.
4. The candidate needs to work well in a team, and with other lab/cleanroom users.
To apply, please visit our website at: https://portal.smart.mit.edu/careers/career-opportunities
Interested applicants are invited to send in their full CV/resume, cover letter and list of three references (to include reference names and contact information). We regret that only shortlisted candidates will be notified