Senior/Engineer, Advanced Packaging Wafer Level Technology Engineering

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD; Singapore; On-site; USD 60,000 - 100,000; Full time

Job summary

An innovative firm is seeking a Post-Fab Wafer Finish Engineer to join their Advanced Packaging Technology Development team. This is a unique opportunity to work at the forefront of semiconductor manufacturing, focusing on process development, quality improvement, and collaboration with various engineering teams. The role emphasizes enhancing wafer finishing processes to meet performance and reliability standards while driving cost efficiency. If you have a strong background in semiconductor processes and a passion for technology, this position offers a chance to contribute to groundbreaking advancements in the industry.

Qualifications

• 2+ years of experience in semiconductor process development.
• Strong understanding of process flows and interactions.

Responsibilities

• Develop and enable processes for post-fab wafer finishing.
• Collaborate with teams for technology development strategies.

Skills

Semiconductor Process Development

Wafer Bonding

Statistical Process Control (SPC)

Data Analysis

Design of Experiments (DOE)

Problem Solving

Education

B.S. in Chemical Engineering

M.S. in Electrical Engineering

Ph.D. in Mechanical Engineering

Job description

Micron’s vision is to transform how the world uses information to enrich life for all. Join a world-class global team focused on one thing: using our expertise in the relentless pursuit of innovation to enable high value technology driven solutions for customers and partners. The solutions we create help make everything from virtual reality experiences to breakthroughs in supercomputing and artificial intelligence possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing.

We are currently experiencing a transformative period in artificial intelligence (AI), where AI is anticipated to become an integral component of daily life. This proliferation is being fueled by advances in memory and compute technologies. High bandwidth memory (HBM) is at the forefront of these innovations. Micron’s Advanced Packaging Technology Development (APTD) is responsible to deliver package development for high performance memory products and transfer to manufacturing.

We are looking for a Post-Fab Wafer Finish (PWF) Engineer to join our Advanced Packaging Technology Development (APTD) team!

Your responsibilities include but are not limited to developing and enabling deployment of processes related to the post-fab wafer finishing processes in semiconductor manufacturing to meet performance, cost, manufacturability, quality, reliability and schedule requirements. You will have opportunity to work with peers and partners across organizations to coordinate the development and launch of new technologies and integration flows for solutions that drive the future.

Key responsibilities and duties include:

Process Development:

• Establish and improve PWF process conditions and technologies (wafer thinning, backside metal interconnect)

• Upgrade process capabilities and reduce production costs

• Establish and improve process management projects to deliver technology node requirements and scaling for next node.

Equipment and Materials:

• Evaluate and promote new equipment and materials to enhance process capabilities

• Set up process parameters for a variety of semiconductor equipment

• Evaluate, promote, and plan for new equipment and materials

Quality Improvement:

• Ensure defense coverage through process, measurement, inspection, and testing

• Establish correlations between defense mechanisms to identify improvement opportunities

• Conduct continuous data analysis to establish advanced controls and identify improvement opportunities

Collaboration and Coordination:

• Work closely with internal and external partners to build and execute technology development strategies aligned with organizational and business objectives

• Work closely with various teams, including the Package Integration, Assembly Engineering, Front End Wafer Fab, Assembly/Test Engineering, Product Engineering, and Global Quality, to integrate manufacturing processes for optimal performance and quality control

• Ensure smooth transition from new product development, qualification, small volume production to high volume production

• Provide Process Of Record (POR) and Model Of Record (MOR) documentation for product transfer to production High Volume Manufacturing Fabrication facilities

Requirements:

• B.S/M.S./Ph.D. (or equivalent education) in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or other related technical fields

• 2 or more years of semiconductor process development, preferably in wafer bonding, plating, warpage control and packaging field

• Strong understanding of process flows, process interactions, and how process changes can affect yield, performance, and reliability

• Experience with design of experiment techniques (DOE), Statistical Process Control (SPC), Defect analysis and data analysis

• Tenacity to work effectively under timelines and limited resources

• Consistent track record to solve problems and address root causes