Director IP Design Engineer - High-Speed Interfaces

Mulya Technologies; Singapore; On-site; SGD 120,000 - 150,000; Full time

Job summary

A leading semiconductor firm is seeking an experienced Director / Principal IP Design Engineer focusing on high-speed interfaces. The candidate will drive the design and validation of cutting-edge IP, ensuring successful silicon outcomes. Ideal candidates possess extensive experience in complex digital and analog designs, particularly with UCIe and PHY designs. Excellent problem-solving and collaboration skills are essential for this senior role.

Qualifications

• 10-20 years of experience in digital, mixed-signal, or analog IP design within the semiconductor industry.
• Proven experience with high-speed interface designs such as UCIe, D2D, DDR PHY, or LPDDR PHY.
• Experience in designing and optimizing PLLs and DLLs.

Responsibilities

• Architect, design, and implement high-speed interface IPs, including UCIe, D2D, DDR, and LPDDR PHYs.
• Develop and optimize PLL and DLL circuits for high-speed clock generation.
• Participate in the complete IP design flow, including architectural definition and RTL coding.

Skills

High-speed interface design

Analog/mixed-signal integration

PLL and DLL design

Problem-solving

Signal integrity knowledge

Team collaboration

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Industry-standard EDA tools

Job description

Director / Principal IP Design Engineer - High-Speed Interfaces

Location: Bangalore

We are seeking a highly skilled and experienced IP Design Engineer to join our team, focusing on the design, development, and validation of cutting-edge high-speed interface Intellectual Property (IP). The ideal candidate will have a strong background in complex digital and mixed-signal design, particularly in interfaces such as UCIe, Die-to-Die (D2D), and various memory PHYs (DDR/LPDDR). Expertise in advanced clocking architectures including PLLs and DLLs is also essential.

This role involves contributing to the full IP development lifecycle, from architectural definition and RTL design to silicon validation and post-silicon support, ensuring first-pass silicon success for critical products that enable next-generation data center interconnects.

Key Responsibilities:

1. Design & Development: Architect, design, and implement high-speed interface IPs, including UCIe, D2D, DDR, and LPDDR PHYs. Develop high-speed SerDes IP transceivers supporting rates like 100G PAM4 (106.25Gbps), 50G PAM4 (53.125 Gbps), and 25G NRZ (26.5625 Gbps) for applications such as PCIe, Ethernet, and data center interconnects.
2. Clocking Design: Develop and optimize PLL and DLL circuits for high-speed clock generation and synchronization, ensuring low jitter and high accuracy. This includes experience with fractional/spread-spectrum/integer frequency synthesizers, LC VCOs, multi-modulus dividers, charge pumps, LPFs, LDO regulators, and BGRs.
3. IP Development Lifecycle: Participate in the complete IP design flow, including architectural definition, specification development, RTL coding, synthesis, static timing analysis (STA), and collaborating on physical design activities (GDSII).
4. Verification & Validation: Work closely with verification teams to define test plans, debug complex design issues, and lead pre-silicon and post-silicon validation efforts, including silicon bring-up and characterization.
5. Additional Features: Implement features for deep in-cable diagnostics (eye metric readout, PRBS bit error rate, loopback modes), fleet management, and security for robust interconnect solutions.
6. Analog/Mixed-Signal Integration: Collaborate on integrating analog and mixed-signal blocks within the PHYs, addressing complex challenges and optimizing for performance, power, and area (PPA).
7. Documentation: Create comprehensive design specifications, integration guidelines, and application notes for IP blocks.
8. Problem Solving: Debug and resolve complex design issues at various development stages, including silicon debugging and fault isolation.
9. Standards Compliance: Ensure IP designs comply with industry standards (e.g., JEDEC for DDR/LPDDR, QSFP-DD/OSFP) and customer requirements.
10. Performance Optimization: Achieve low-latency data paths (< 100 ns) and optimize for lower power consumption in high-speed interconnects.

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field.
• 10-20 years of experience in digital, mixed-signal, or analog IP design within the semiconductor industry.
• Proven experience with high-speed interface designs such as UCIe, D2D, DDR PHY, or LPDDR PHY.
• Experience in designing and optimizing PLLs and DLLs, including various frequency synthesizers and clock generation circuits.
• Familiarity with the entire IP development flow from architectural concept to silicon validation.
• Strong understanding of signal integrity, power integrity, and high-speed layout considerations.
• Proficiency with industry-standard EDA tools for design, simulation, and analysis.
• Experience with deep diagnostic features, security implementations, and firmware security.
• Excellent problem-solving, communication, and collaboration skills.

Contact: Uday, Mulya Technologies, hidden_email