Digital IC Verification Engineer

ESPRESSIF SYSTEMS (SINGAPORE) PTE. LTD.; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

A leading company specialized in semiconductor design is looking for a Verification Engineer to develop and execute verification plans for their chip designs. The role involves collaborating with design and FPGA teams, ensuring the integrity of chip designs, and requires expertise in relevant software languages and methodologies. Ideal candidates will have hands-on experience in verification environments and a strong educational background in engineering.

Qualifications

• Bachelor's degree or higher in relevant fields required.
• Experience in design or verification of communication modules/SoCs essential.
• Knowledge of UVM and formal verification is a plus.

Responsibilities

• Develop verification plans and execute regression testing.
• Collaborate with chip design engineers to resolve design defects.
• Perform RTL-level and low-power verification.

Skills

Proficiency in Verilog

Expertise in C/SystemVerilog

Knowledge of scripting languages

Education

Bachelor’s degree in Computer Science

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Communications Engineering

Job description

Job Description

• Develop verification plans based on design-related documentation, set up the verification environment, and complete verification from module level to system level.
• Execute regression testing and enhance verification coverage.
• Collaborate with chip design engineers to identify and resolve design defects.
• Guide the design team in implementing a verification-friendly design flow.
• Perform RTL-level, gate-level, and low-power verification with UPF (Unified Power Format).
• Assist FPGA engineers and software engineers in completing FPGA prototype testing.
• Ensure the integrity and correctness of chip designs from multiple dimensions.

Requirements

• Bachelor’s degree or higher in Computer Science, Electrical Engineering, Communications Engineering.
• Experience in design or verification of peripheral modules, communication modules, or SoC systems.
• Proficiency in Verilog and expertise in C/SystemVerilog.
• Knowledge of one or more scripting languages such as Python, Ruby, Perl, Shell, Tcl, or Makefile.
• Experience with UVM (Universal Verification Methodology) is a plus.
• Familiarity with the digital chip development process and successful tape-out project experience is an advantage.
• Experience with formal verification is a plus.