DFT Engineer (Design-For-Test)

VOICE THE WAY PTE. LTD.; Singapore; On-site; USD 60,000 - 100,000; Full time

Job summary

An innovative firm is seeking a skilled engineer to drive the architecture and implementation of cutting-edge DFT features for SoC/IP designs. This role involves researching state-of-the-art methodologies, developing in-house automation flows, and performing yield analysis to enhance product performance. Join a team dedicated to pushing the boundaries of technology and contribute to exciting projects that shape the future of integrated circuits. If you are passionate about design and testing in the semiconductor industry, this opportunity is perfect for you!

Qualifications

• Experience in DFT methodologies for SoC/IP designs.
• Strong background in yield analysis and troubleshooting.

Responsibilities

• Participate in DFT feature architecture and implementation for SoC/IP.
• Conduct yield analysis and troubleshoot DFT-related issues.

Skills

DFT (Design-For-Test)

Scan Chain Design

ATPG

Pattern Generation

Simulation

Diagnosis

Yield Analysis

Troubleshooting

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Computer Engineering

Tools

DFT Automation Tools

Simulation Software

Job description

Responsibilities:

1. Participate in the architecture and implementation of DFT (Design-For-Test) features for SoC/IP, including scan chain design, ATPG, pattern generation, simulation, and diagnosis.
2. Perform CP (wafer-level) and FT (final test) yield analysis based on diagnosis results.
3. Research and evaluate state-of-the-art DFT architectures and methodologies for SoC/IP designs.
4. Develop and maintain in-house DFT flows and automation methods, and deploy them across multiple projects.
5. Troubleshoot DFT-related issues during design implementation and silicon bring-up phases.