Design Verification Engineer (SoC Design/ASIC/UVM/OVM/RTL)

HKM HR MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 70,000 - 120,000; Full time

Job summary

A technology firm in Singapore seeks an experienced engineer to handle SoC verification tasks. This role requires a Master's or PhD in Electrical Engineering with extensive experience in UVM/OVM and various programming languages. The engineer will create test plans, manage verification environments, and mentor junior team members. Interested candidates can apply via the provided email.

Qualifications

• Master's or PhD in Electrical Engineering with relevant experience.
• Extensive understanding of UVM/OVM and verification methodology.
• Experience with design verification at RTL and post-P&R levels.

Responsibilities

• Create and document detailed test plans for SoC verification.
• Manage infrastructure for automated verification.
• Develop reusable testbenches and cases for verification.

Skills

Verilog

SystemVerilog

Python

Perl

TCL

Shell scripting

C/C++

SystemC

assertion-based verification

UVM/OVM

Education

Master in Electrical Engineering or equivalent with 8 years of experience

PhD in Electrical Engineering or equivalent with 3 years of experience

Job description

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

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HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [e-mail] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628