Design Verification Engineer (SOC/ASIC/Verilog)

HKM HR MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 65,000 - 90,000; Full time

Job summary

A leading company in Singapore is seeking a Verification Engineer to work closely with design teams on SoC verification. The role requires expertise in verification methodologies and significant experience in a related field. You will be responsible for developing test plans, managing environments, and guiding junior engineers to enhance verification processes.

Qualifications

• Master or PhD in Electrical Engineering with several years of relevant experience.
• Extensive understanding of verification methodologies and tools.
• Experience in verifying designs at RTL and post-P&R gate levels.

Responsibilities

• Develop detailed test plans and manage automated verification environments.
• Create reusable testbenches and strategies for comprehensive coverage.
• Collaborate with engineers to troubleshoot simulation issues and mentor team members.

Skills

UVM/OVM

Semiformal Verification

Assertion-based verification

Hardware-software co-verification methodology

Verilog

SystemVerilog

Python

Perl

TCL

Shell scripting

C/C++

SystemC

Assembly coding

Education

Master in Electrical Engineering or equivalent

PhD in Electrical Engineering or equivalent

Tools

MIPI

AMBA (APB/AHB/AXI)

RISC-V

ARM

DSP cores

Job description

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

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HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [e-mail] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628