Design Verification Engineer (SOC/ASIC/UVM/OVM)

HKM HR MANAGEMENT PTE. LTD.; Singapore; On-site; SGD 80,000 - 120,000; Full time

Job summary

Une entreprise leader dans le domaine de l'ingénierie recherche un ingénieur en validation SoC pour rejoindre leur équipe dynamique à Singapour. Le candidat idéal aura une solide expérience en vérification automatisée et une compréhension approfondie des méthodologies de vérification avancées. Il travaillera étroitement avec les ingénieurs de conception pour garantir l'intégrité des conceptions et formera les membres juniors de l'équipe. Des compétences en UVM/OVM et la maîtrise de plusieurs langages de programmation sont essentielles.

Qualifications

• Master ou PhD en ingénierie électrique requis avec expérience pertinente.
• Expérience de 8 ans ou 3 ans après un PhD nécessaire.
• Compréhension approfondie des méthodologies de vérification.

Responsibilities

• Établir et gérer l'infrastructure pour la vérification automatisée.
• Développer des banques de tests réutilisables et des cas de test.
• Collaborer avec des ingénieurs pour résoudre les problèmes de simulation.

Skills

UVM/OVM

Verilog

SystemVerilog

Python

Perl

TCL

Shell scripting

C/C++

SystemC

Education

Master in Electrical Engineering

PhD in Electrical Engineering

Job description

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.
  

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

__________________________________________________________

HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact [e-mail] for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628