Back-End IC Engineer

WATT AI PTE. LTD.; Singapore; On-site; USD 70,000 - 110,000; Full time

Job summary

An innovative high-tech company is seeking talented IC Architects to join their team. This role involves applying cutting-edge design methodologies to deliver state-of-the-art designs for advanced technology nodes. You will work closely with experts in the field to enhance AI chip development and contribute to groundbreaking projects. The ideal candidate will possess a strong background in backend digital design and EDA tools, with the opportunity to influence the future of AI technology. Join a team where your expertise can lead to significant advancements in the industry.

Qualifications

• Master's degree in relevant field required; PhD preferred.
• Deep understanding of backend digital design flow essential.

Responsibilities

• Integrate SoC for physical design in advanced technologies.
• Build and adapt automation flows for design processes.

Skills

Backend digital design flow

Timing constraints

Physical constraints

Scripting languages (Tcl, Perl)

Education

Master’s Degree in EE, CS, Math, Physics

PhD in related subjects

Tools

EDA tools (Genus, Innovus, Quantus, Tempus)

DC/Star-RCXT/PrimeTime

PrimeRail/Voltus

Redhawk

Job description

Headquarter in Singapore, WATT AI PTE LTD (www.wattai.tech) is an innovative high-tech company co-founded by hardware and software experts working on next-gen AI processors (ASICs) and models and GPU cloud from Silicon Valley. It is committed to developing high-performance AI chips and computing clusters that support ultra-large-scale AI model training. We are looking to grow our team with the most intelligent people of the world. Together, we can really make a change.

Position: IC Architects (3-4 full-time headcounts)

Directly reporting to co-founder & CTO.

Job Scope

As a Back-End IC Engineer, you will apply the latest design methodology and milestone flow to deliver state-of-the-art design over advanced technology node from RTL to GDSII. You should have very good experience in layout activities of block and level, including floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.

Responsibilities

1. Understanding of SoC for top-down/bottom-up physical design integration in advanced technologies.
2. Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows.
3. Must have knowledge of P&R, Extraction, Physical Verification, STA, ECO.
4. Build automation flows wherever needed/adapt to existing flows for re-use.

Key Qualifications

1. A Master’s Degree in EE, CS, Math, Physics or related subjects, PhD preferred.
2. A deep understanding of backend digital design flow.
3. Proficient in timing constraints, physical constraints.
4. Proficient in handling EDA tools across floorplan/partition/placement/CTS/route stages for SoC top-level.
5. Proficient with backend EDA tools Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PrimeTime, PrimeRail/Voltus, Redhawk.

Preferred Qualifications

1. Proficiency in scripting languages (e.g., Tcl, Perl).