Senior Verification Enigneer

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Senior Verification Engineer - Specialised ASIC Design House - West Austria

A successful chip design house in Austria is looking to hire a Senior Verification Engineer to join their international team.

They offer a wide range of specialised Engineering services used in automotive, audio, industrial, security, and wireless markets. You will have the opportunity to work on complex and challenging projects, collaborating closely with other teams in Europe.

Key Skills:

• Experience in UVM
• Worked on successful and complex ASIC projects
• Knowledge of a programming language (Verilog or SystemVerilog)
• Understanding of RTL design
• Fluent in English

If you are interested in applying or would like to find out more, please contact Lucy Edmondson.