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Luxoft Poland is building a hardware-assisted security platform that detects threats at the processor level. You will own the technical architecture for the full stack, including PMU/IBS kernel driver, ML inference, and partner SDK, collaborating with silicon, driver, ML and CI/CD teams.
This leadership role requires 12+ years of engineering with 5+ years in leadership, and KPIs for detection-efficacy and performance budgets.
The Client's building a hardware-assisted security platform that uses silicon-level Performance Monitoring Counters (PMCs) and on-chip machine learning to detect advanced endpoint threats (ransomware, fileless malware, cryptojacking) at the processor layer, below OS-based evasion. The platform collects CPU behavioral telemetry, classifies it via an ML inference engine, and exposes threat signals to security-software partners through a standardized API. The team covers the full stack: silicon telemetry, ML training/validation, real-time inference, lab qualification and CI/CD.
Own the technical architecture for the full hardware threat-detection platform (PMU/IBS kernel driver, ML inference pipeline, partner SDK, HW attestation).
Set and enforce technical quality standards: detection-efficacy KPIs (detection rate, false-positive rate), performance budgets (CPU overhead), API backward-compatibility.
Lead cross-functional architectural decisions across silicon, driver, ML and real-time pipeline.
Own the partner SDK strategy and the technical relationship with security-software integration partners.
Lead efficacy validation gates across the malware variant test suite. Mentor SMTS-level engineers across lab, ML, real-time and CI/CD. Represent the platform in external technical forums and partner engagements.
Identify and mitigate program-level technical risks.
12+ years progressive engineering experience with 5+ years in a technical leadership or principal engineering role.
Deep expertise in at least two of: CPU microarchitecture & performance monitoring; ML systems & inference pipeline engineering; systems software & kernel development; endpoint security platform architecture. Experience leading multi-disciplinary efforts inception-to-production. Excellent communication across executive, partner and engineering audiences.
Experience defining program-level KPIs and quality gates.
Hardware-assisted security technology on any major processor architecture.
Endpoint security research, malware analysis or threat intelligence at enterprise scale.
AMD silicon or AMD security processor technology.
Patent portfolio or publications in hardware security or ML for security. Experience managing external security-software partner technical programs (joint engineering, certification, go-to-market).