Principal Engineer / Technical Team Lead, Hardware Security Platform

Luxoft DXC; Województwo pomorskie; On-site; PLN 300,000 - 420,000; Full time

Job summary

AMD is building a hardware-assisted security platform that leverages silicon-level PMCs and on‑chip ML to detect advanced endpoint threats on Windows 11 endpoints. The Technical Team Lead will own the end‑to‑end technical direction, coordinating CPU telemetry, Windows software, ML inference, and partner SDK/API integration in a hands‑on principal engineering role.

The role emphasizes architecture ownership, technical leadership, and cross‑functional delivery, with regular on‑site work in Gdańsk.

Qualifications

• Experience leading end-to-end architecture of hardware-assisted threat-detection platforms.
• Regular on-site work in Gdańsk.
• Strong collaboration across hardware, software, ML, and security teams.

Responsibilities

• Own the end-to-end technical architecture of the platform, covering CPU telemetry, Windows components, ML inference, and SDK/API integration.
• Define technical strategy, architectural boundaries, interfaces, and integration models across workstreams.
• Lead cross-functional architectural decisions involving telemetry, Windows components, ML, and endpoint-security requirements.
• Establish and maintain technical quality standards, architecture principles, design-review practices, and engineering acceptance criteria.
• Define measurable efficacy and performance objectives, including detection quality, latency, overhead, and API compatibility.
• Lead evaluation of trade-offs between model quality, telemetry coverage, runtime performance, and resource usage.
• Own the technical strategy for the partner-facing SDK/API with stability and versioning considerations.
• Coordinate the technical relationship with approved security-software integration partners.
• Lead end-to-end validation gates across workloads, threat categories, and configurations.
• Document decisions, interfaces, risks, and limitations for traceability.
• Identify and mitigate program-level risks and cross-workstream dependencies.
• Provide hands-on technical guidance across hardware, drivers, systems software, ML, and security.
• Mentor senior engineers across labs and workstreams.
• Represent the platform in client architecture reviews and external engagements.
• Translate progress and risks into clear decisions and priorities.
• Support transition from PoC to scalable productization.

Skills

Technical leadership

Architecture ownership

Mentorship

Hands-on engineering

Tools

Windows kernel

SDK/API integration

Job description

AMD is building a hardware-assisted security platform that uses silicon-level Performance Monitoring Counters (PMCs) and on‑chip machine learning to detect advanced endpoint threats, including ransomware, fileless malware, and cryptojacking, at the processor layer, below OS-based evasion, on a Windows 11 endpoint platform.

The platform collects CPU behavioral telemetry, classifies it through an ML inference engine, and exposes threat signals to security-software partners through a standardized API.

The project covers the full engineering path from silicon telemetry and data generation through ML training and validation, low‑latency Windows runtime integration, lab qualification, and partner integration.

The Technical Team Lead will own the end‑to‑end technical direction of the platform and coordinate decisions across CPU telemetry, Windows systems software, machine learning, security validation, and partner‑facing interfaces. This is a hands‑on principal engineering role combining architecture ownership, technical leadership, and cross‑functional delivery.

The role requires regular on‑site work in Gdańsk. Additional implementation details will be shared during the recruitment process in line with the applicable confidentiality requirements.

• Own the end‑to‑end technical architecture of the hardware‑assisted threat‑detection platform, covering CPU telemetry collection, Windows systems components, ML inference, partner‑facing SDK/API integration, and platform security mechanisms.
• Define the technical strategy, architectural boundaries, interfaces, and integration model across the Lab, ML, and Real‑Time workstreams.
• Lead cross‑functional architectural decisions involving processor telemetry, Windows kernel and user‑space components, model inference, system performance, endpoint‑security requirements, and partner integration.
• Establish and maintain technical quality standards, architecture principles, design‑review practices, and engineering acceptance criteria.
• Define measurable efficacy and performance objectives, including detection quality, false‑positive behavior, inference latency, system overhead, reliability, and API compatibility.
• Lead technical evaluation of trade‑offs between model quality, telemetry coverage, runtime performance, implementation complexity, and system resource consumption.
• Own the technical strategy for the partner‑facing SDK/API, including interface stability, versioning, compatibility, diagnostics, and integration guidance.
• Coordinate the technical relationship with approved security‑software integration partners.
• Lead end‑to‑end validation gates across representative workloads, threat categories, system configurations, and hardware platforms.
• Ensure that technical decisions, interfaces, assumptions, risks, and known limitations are documented and traceable.
• Identify, communicate, and mitigate program‑level technical risks and cross‑workstream dependencies.
• Provide hands‑on technical guidance and design support when complex issues span hardware, drivers, systems software, ML, and security.
• Mentor senior engineers across the Lab, ML, and Real‑Time workstreams and help them resolve cross‑disciplinary technical problems.
• Represent the platform in client architecture reviews, partner discussions, and approved external technical engagements.
• Work with project stakeholders to translate technical progress, constraints, and risks into clear decisions and priorities.
• Support the transition from Proof of Concept toward a scalable productization architecture if the initial phase is successful.