Lead Architect - Hardware Security Platform & ML

Luxoft; Poland; On-site; PLN 360,000 - 600,000; Full time

Benefits offered by this job

Private medical & dental care

Life Insurance

Internal mobility program

Job summary

Luxoft is seeking a senior engineering leader to own the hardware threat-detection platform architecture, spanning PMU/IBS kernel driver, ML inference pipeline, and partner SDKs. The role involves setting quality gates, guiding cross-functional decisions across silicon, driver, ML and real-time components.

The candidate will mentor engineers, drive KPI-based validation, and represent the platform in external technical forums and partner engagements.

Qualifications

• 12+ years progressive engineering experience with 5+ years in a technical leadership or principal engineering role.
• Deep expertise in CPU microarchitecture & performance monitoring; ML systems & inference pipeline engineering.
• Experience leading multi-disciplinary efforts from inception to production.
• Excellent communication across executive, partner and engineering audiences.
• Experience defining program-level KPIs and quality gates.

Responsibilities

• Own the technical architecture for the full hardware threat-detection platform (PMU/IBS kernel driver, ML inference pipeline, partner SDK, HW attestation).
• Set and enforce technical quality standards: detection-efficacy KPIs, CPU overhead budgets, API backward-compatibility.
• Lead cross-functional architectural decisions across silicon, driver, ML and real-time pipeline.
• Own the partner SDK strategy and the technical relationship with security-software integration partners.
• Lead efficacy validation gates across the malware variant test suite; mentor engineers across lab, ML, and CI/CD; represent the platform in external forums.

Skills

Senior leadership

CPU microarchitecture

ML systems

kernel development

KPIs & quality gates

Job description

Luxoft is seeking a senior engineering leader to own the hardware threat-detection platform architecture, spanning PMU/IBS kernel driver, ML inference pipeline, and partner SDKs. The role involves setting quality gates, guiding cross-functional decisions across silicon, driver, ML and real-time components.

The candidate will mentor engineers, drive KPI-based validation, and represent the platform in external technical forums and partner engagements.