DFT Lead, Semiconductors — Hybrid, Multisite Role

Capgemini; Polska; Hybrid; PLN 180,000 - 300,000; Full time

Benefits offered by this job

Well-being culture

Training tracks on NEXT platform

Hybrid working model

Performance feedback discussions

Home office package

Job summary

Capgemini Engineering in Poland seeks a DFT Lead to drive design-for-test across multiple locations including Wrocław, Gdańsk, Opole, Bydgoszcz, Katowice, Warszawa, Lublin, Kraków and Poznań. You will implement robust DFT flows, collaborate with design teams, and guide a multinational group of engineers to improve test coverage and timing at scale.

The role demands 6+ years in DFT/test flows with EDA tools, strong JTAG/ATPG/MBIST knowledge, scripting skills, and a hands-on problem-solving

Qualifications

• 6+ years of hands-on DFT/test-flow experience with commercial EDA tools for large SOCs.
• Strong knowledge of JTAG, ATPG, yield learning, logic diagnosis, and MBIST/LBIST.
• Experience with Synopsys DFT Compiler, Tetramax, VCS, Tessent or Modus/Encounter tool suite.
• RTL simulation, synthesis, Linting, CDC/RDC checks, STA, and DFT metrics is a plus.
• Proficient in Perl/Tcl/Python scripting.
• Excellent analytical and problem-solving skills.

Responsibilities

• DFT implementation inline with test methodology for advanced process nodes.
• Perform top- and block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST.
• Collaborate with physical design team to resolve timing constraints/issues.
• Verify DFT circuitry and interface with IPs; debug timing simulations.
• Diagnose and improve DFT KPIs: test coverage, pattern efficiency.
• Opportunity to lead a multilocational team of DFT engineers.

Skills

DFT techniques

JTAG

ATPG

MBIST/LBIST

yield learning

logic diagnosis

IEEE 1500

RTL simulation

Perl scripting

Python scripting

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Job description

Capgemini Engineering in Poland seeks a DFT Lead to drive design-for-test across multiple locations including Wrocław, Gdańsk, Opole, Bydgoszcz, Katowice, Warszawa, Lublin, Kraków and Poznań. You will implement robust DFT flows, collaborate with design teams, and guide a multinational group of engineers to improve test coverage and timing at scale.

The role demands 6+ years in DFT/test flows with EDA tools, strong JTAG/ATPG/MBIST knowledge, scripting skills, and a hands-on problem-solving