Senior Design Verification Engineer

10xengineers; Lahore; On-site; PKR 1,500,000 - 2,000,000; Full time

Job summary

A prominent semiconductor design firm in Lahore is seeking a Verification Engineer to join their team. The role involves developing test plans, collaborating with teams on IP design verification, and contributing to process improvements. The ideal candidate has over 4 years of experience and expertise in RISC V assembly language and related technologies. This position offers the chance to work in a fast-paced and collaborative environment.

Qualifications

• 4+ years of working experience in verification.
• Experience in testplan development and implementation.
• Hands-on experience with RISC V Priv/Unpriv architecture.

Responsibilities

• Develop and execute testplans for complex IPs.
• Collaborate with design and verification teams.
• Utilize advanced verification methodologies.

Skills

RISC V assembly language expertise

C language proficiency

Collaboration skills

Problem-solving skills

Attention to detail

Education

Bachelor’s or Master’s degree in Computer Science or Electrical Engineering

Tools

Verilog/System Verilog

Industry-standard verification tools

Job description

Experience Required: 4+ years
Location: Lahore, on-site
Job Type: Full-time
Industry: Semiconductor, Design Verification

We are looking for a self-motivated engineer who will be part of our verification team. In this role, you will work closely with the designers and verification team on complex IP design verification. You will be responsible for testplan development and implementation, debugging failure, and responsible for coverage closure.

This is an exciting opportunity to work with an experienced and highly motivated team of verification engineers.

Key Responsibilities:

• Developing and executing testplans for complex IPs
• Collaborate with the design and verification teams to ensure comprehensive coverage.
• Utilize advanced verification methodologies to identify and resolve design issues.
• Contribute to the continuous improvement of verification processes and methodologies.
• Participate in code reviews and provide feedback on verification-related aspects.
• Maintain thorough documentation of verification activities and results.
• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field
• 4+ years of working experience

Mandatory Skills:

• RISC V assembly language and C language expertise for low level programming
• Hands of experience with RISC V Priv/Unpriv architecture is must
• Good understanding computer architecture concepts
• Experience with hypervisors and virtualization is add plus
• Experience with testplan development and implementation
• Knowledge of Verilog/System Verilog
• Familiarity with industry-standard verification tools
• Ability to work in a fast-paced and collaborative environment
• Strong communication and collaboration abilities
• Excellent problem-solving skills and attention to detail.

Desired Skills:

• Expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM).
• Proficiency in testbench development and verification methodologies.
• Strong understanding of the verification life cycle.
• Good understanding of advance computer architecture concepts such as Branch predication, out-of-order processors, cache coherency, memory consistency models
• Contributions to RISC-V open-source projects such as arch-test development