Senior Physical Design Engineer

Chinese American Semiconductor Professional Association; San Jose; Hybrid; PHP 6,264,000 - 9,716,000; Full time

Job summary

A leading semiconductor company is seeking a Senior Physical Design Engineer to drive physical design implementations for advanced process nodes. Responsibilities include netlist-to-GDS flow, PPA optimizations, and CAD tool development. Candidates should have a Master's degree in Electrical Engineering or Computer Science, along with at least 4 years of relevant experience. The role offers a hybrid work schedule based in San Jose, California, with competitive compensation ranging from $108,000 to $167,500 annually.

Qualifications

• Minimum 4 years of relevant industry experience.
• In-depth knowledge of VLSI design and digital integrated circuits.
• Experience with physical design implementation flows.
• Ability to program in Python/Perl/TCL and CSH script.

Responsibilities

• Implement physical design on TSMC’s advanced process nodes.
• Conduct netlist-to-GDS flow and optimize PPA.
• Analyze cell library utilization and congestion data.
• Develop CAD tools for design flow and scripting.

Skills

Knowledge of hardware design courses

Python programming

Problem-solving skills

Communication skills

Education

Master's degree in Electrical Engineering or Computer Science

Tools

EDA tools

Job description

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison, congestion & DRC analysis, and design optimization. You may also do synthesis, debugging & data analysis, scripting, STA or timing analysis. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, California and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office.

Responsibilities

• Responsible for the physical implementation on TSMC’s most advanced process nodes.
• Netlist-to-GDS flow including block/soc-level placement, clock tree synthesis, routing, and design optimization.
• Evaluate flow and methodologies to optimize power, performance, and area (PPA).
• Analyze standard cell library utilization and route congestion data.
• CAD development including customizing design flows and creating comparison tables using scripting language such as TCL, Python, Perl and Shell.

Minimum Qualifications

• Master’s degree in Electrical Engineering or Computer Science with a minimum of 4 years of relevant industry experience.
• In depth knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
• Knowledge on physical design implementation flows, auto placement and routing (APR), static timing analysis (STA), layout design, physical design verification (PDV), IREM signoff, and CAD development.
• Experiences in research projects or internship related to RTL coding, synthesis, digital design and testing, physical implementation or design verification
• In depth knowledge of major EDA tools/design flows.
• Experience in Python/Perl/TCL language programming and CSH script.
• Ability to work regularly at a customer site in the South Bay area.

Preferred Qualifications

• Able to independently complete Netlist-GDS P&R.
• Excellent communication skills and strong problem-solving skills.
• Positive, Active, Collaborative, Self-motivated, Adaptable and Flexible.
• TSMC N16 and below technology.
• Experience in software programming is a plus.

Company Description

TSMC is a trusted technology and capacity provider, driven by the desire to be the world’s leading dedicated semiconductor foundry, the technology leader with a strong reputation for manufacturing excellence, and to advance semiconductor manufacturing innovations to enable the future of technology.

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.

Diversity statement

TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law. TSMC is an equal opportunity employer prizing diversity and inclusion.

Pay Transparency Statement

At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $108,000/yr and $167,500/yr. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual’s skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses and comprehensive benefits.