Memory Design Engineer - SRAM & IP (Hybrid)

Arm Limited; Hinoba-an; Hybrid; PHP 600,000 - 1,000,000; Full time

Job summary

Arm Limited's Physical IP Division seeks a memory design engineer to contribute to memory fast cache instances, working on design, margining, characterization, verification and release of memory IPs. You will engage with Verilog, liberty, schematics, LEF and GDSII views and learn automation techniques to improve the verification flow.

This role offers exposure to cutting-edge technologies and a hybrid working model designed to balance performance and wellbeing, with collaboration across teams

Qualifications

• Bachelors or Master’s Degree in Electronics Engineering with excellent academic credentials
• 2–5 years experience in Memory design or characterization
• Strong understanding of SRAM, digital circuits fundamentals and SOC concepts
• Experience with Verilog, Liberty, schematics, LEF and GDSII is preferred

Responsibilities

• Design, margining, characterization, verification and release of Memory instances
• Work with Verilog, liberty, schematics, lef and gds views and associated EDA tools
• Learn automation techniques for development and verification flows

Skills

Memory design

Characterization

Scripting (Shell, TCL)

Education

Bachelor's or Master's Degree in Electronics Engineering

Tools

Verilog

Liberty

Schematic

LEF

GDSII

Job description

Arm Limited's Physical IP Division seeks a memory design engineer to contribute to memory fast cache instances, working on design, margining, characterization, verification and release of memory IPs. You will engage with Verilog, liberty, schematics, LEF and GDSII views and learn automation techniques to improve the verification flow.

This role offers exposure to cutting-edge technologies and a hybrid working model designed to balance performance and wellbeing, with collaboration across teams