Junior Design Verification Engineer (SystemVerilog/UVM)

Analog Devices; Cavite City; On-site; PHP 300,000 - 500,000; Full time

Benefits offered by this job

Mentorship program

Continuous learning opportunities

Job summary

Analog Devices, a global semiconductor leader, invites applications for an Associate Design Verification Engineer. You will develop test benches and perform design verification of new digital, analog, and mixed-signal products prior to tape-out.

This entry-level role focuses on learning and development while working under close direction with regular review. You'll gain hands-on experience with verification methodologies and tools under senior guidance.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 0-2 years of relevant experience; new graduates welcome to apply.
• Fundamental knowledge of digital design verification concepts.

Responsibilities

• Develop and execute basic test benches for mixed-signal product verification.
• Create and maintain basic test environments using SystemVerilog/UVM.
• Conduct code coverage analysis to ensure design accuracy.
• Debug simulation failures and track coverage metrics.
• Support verification planning and documentation.
• Collaborate with design teams to understand requirements.
• Identify potential design issues under guidance of senior team members.
• Document verification processes and results.

Skills

SystemVerilog

UVM

Python

Verilog RTL

Digital Interfaces

Simulation Tools

Problem Solving

Communication

Education

Bachelor's degree in Electrical Engineering or related field

Tools

SystemVerilog/UVM

Job description

Analog Devices, a global semiconductor leader, invites applications for an Associate Design Verification Engineer. You will develop test benches and perform design verification of new digital, analog, and mixed-signal products prior to tape-out.

This entry-level role focuses on learning and development while working under close direction with regular review. You'll gain hands-on experience with verification methodologies and tools under senior guidance.