FPGA Design Engineer

KaleidEO Analytics India Pvt. Ltd.; Hinoba-an; On-site; PHP 600,000 - 900,000; Full time

Benefits offered by this job

Medical health cover

Family leave policies

International conferences

Mental health support

Learning allowances

Job summary

KaleidEO Analytics India Pvt. Ltd. seeks an FPGA Engineer to design, develop, and test FPGA-based solutions with emphasis on radiation tolerance, timing analysis, and debugging. The role covers AXI/AMBA protocols, DDR/NAND memory, and integration with Xilinx FPGAs in both standalone and embedded contexts.

You will collaborate with ex-ISRO scientists and global space industry experts to advance high-reliability EO payloads and edge computing capabilities in a fast-growing upstream company.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 2-3 years of hands-on FPGA development experience.
• Experience with radiation-tolerance techniques is a plus.

Responsibilities

• Design, develop, and test FPGA-based solutions using VHDL/Verilog or SystemVerilog.
• Implement communication interfaces such as AXI, AHB, or APB in ARM-based SoC environments.
• Integrate and verify memory interfaces including DDR and NAND flash.
• Support design for radiation tolerance and SEU mitigation (e.g., TMR, EDAC).
• Perform timing analysis, simulation, and debugging using industry tools.
• Work with Xilinx and Microchip FPGAs in standalone and embedded contexts.
• Document design specifications, test plans, and verification results.

Skills

FPGA architecture

Digital design

AXI/APB/AMBA

DDR/NAND memory

Xilinx Vivado

ModelSim/debugging

Timing closure

Education

Bachelor’s or Master’s in Electronics/ECE/CompEng

Tools

Vivado

ModelSim

Libero SoC

SDK/Vitis

Job description

Work with the brightest minds, including ex-ISRO scientists and global space industry experts, at one of the select few companies in the country pioneering cutting edge EO payloads.

Seeking an FPGA Engineer to design, develop, and test FPGA-based solutions with a focus on radiation tolerance, timing analysis, simulation, and debugging.

About KaleidEO

KaleidEO, a subsidiary of SatSure, is an upstream leader in Earth Observation, building a full-stack company from India.

As an analytics-first payload innovator, we focus on building next-gen payloads tailored for industry-specific applications.

Our high-resolution, optical, multispectral payloads, equipped with edge computing and wide coverage capabilities, maximize the value generated from every pixel of satellite imagery.

Rooted in SatSure’s legacy of delivering last-mile applications across sectors like Utilities, Aviation, Agriculture, BFSI and Climate Action, KaleidEO offers modular solutions for the entire EO value chain spanning payload development, launch, mission operations, and data analytics

At KaleidEO, we are committed to shaping the future of Earth Observation and putting Indian space tech on a global map, and we invite you to be part of this exciting journey.

Roles andResponsibilities

• Design, develop, and test FPGA-based solutions using VHDL/Verilog or SystemVerilog.
• Implement communication interfaces such as AXI, AHB, or APB in ARM-based SoC environments.
• Integrate and verify memory interfaces including DDR, NAND Flash, and other external memory types.
• Support design for radiation tolerance, SEU mitigation techniques (e.g., TMR, EDAC), and fault detection.
• Perform timing analysis, simulation, and debugging using industry-standard tools (e.g., Vivado, ModelSim, Libero SoC).
• Work with Xilinx and Microchip FPGAs in both standalone and embedded contexts.
• Document design specifications, test plans, and verification results.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field .
• 2-3 years of hands-on experience in FPGA deve

Must have

• Strong understanding of FPGA architecture and digital design principles.
• Proficient with ARM-based protocols such as AXI, AHB, and APB.
• Experience with memory interfaces like DDR (DDR3/DDR4) and NAND flash is a plus.
• Familiar with Xilinx toolchains (Vivado, SDK/Vitis) and Microchip tools (Libero SoC).
• Ability to read and interpret hardware schematics and timing diagrams.
• Experience with simulation and debugging tools (e.g., ModelSim, Vivado Logic Analyzer).
• Solid grasp of timing closure, floor planning, and resource optimization.

Good to have

• Exposure to high-speed serial interfaces (e.g., PCIe, Ethernet).
• Experience in scripting (Tcl, Python, or Shell) for automation.
• Knowledge of embedded software development and driver integration.
• Knowledge of SEU mitigation techniques and fault detection techniques.

Interview Process

• Introductory call
• Panel Interview rounds ( 2 rounds)

No of positions: 1

Medical Health Cover for you and your family including unlimited online doctor consultations

We believe family comes first. That’s why we offer Maternity, Paternity, Marriage and Bereavement Leave, so you can be there when it matters most.

We ensure every member of the team gets an opportunity to participate at international events and conferences.

Access to mental health experts for you and your family.

Dedicated allowances for learning and skill development.