Senior IC Layout Engineer

IC Resources; Delft; On-site; EUR 70,000 - 90,000; Full time

Benefits offered by this job

Collaborative working environment

Technically challenging projects

Job summary

A semiconductor design company near Delft is seeking a Senior IC Layout Design Engineer. The role involves extensive experience in analog and digital layout design, leading chip planning, and mentoring junior engineers. Candidates should have a strong background in CMOS and BiCMOS technologies and be proficient in Cadence Virtuoso. This position requires 5 days on-site work.

Qualifications

• Extensive experience in analog and full custom digital layout.
• Lead top-level chip planning and deliver block-level layout.
• Mentor junior engineers and offshore layout contractors.

Responsibilities

• Conduct top-level and block-level layout for analog and digital blocks.
• Perform layout verification, including DRC, LVS, and ERC.
• Support chip-level integration and tape-out.

Skills

Layout design for analog and digital circuits

Proficient with Cadence Virtuoso

Understanding of layout effects

Education

6-12 years of relevant experience

Tools

DRC/LVS/ERC tools (PVS or Calibre)

Job description

3 days ago Be among the first 25 applicants

Direct message the job poster from IC Resources

Analog IC / RF IC Recruitment by day / Unity Game Developer by night

I am recruiting for a Senior IC Layout Design Engineer to join my client's design centre based near Delft, Netherlands.

My client is looking for a Senior IC Layout Design Engineer with extensive experience in analog and full custom digital layout for CMOS and BiCMOS technologies. You will lead top-level chip planning, deliver block-level layout, and support chip integration and tape-out. The role also includes mentoring junior engineers and offshore layout contractors, helping to develop consistent layout methodologies and workflows across sites.

Key responsibilities:

• Top-level and block-level layout for analog and digital blocks
• Schematic driven layout and constraint-based design
• Chip level floorplanning, power distribution, shielding and device matching
• Layout verification including DRC, LVS, and ERC
• Chip-level integration and support for tape-out
• Training and guidance for junior and offshore layout engineers

Key requirements:

• 6-12 years' experience in layout design for analog and digital circuits
• Strong background in CMOS and BiCMOS, ideally including TSMC 180nm, 65nm, and 22nm nodes
• Proficient with Cadence Virtuoso and familiar with DRC/LVS/ERC tools (PVS or Calibre)
• Solid understanding of layout effects including parasitics, matching, EM, IR drop and crosstalk
• Familiarity with layout automation and scripting tools is a plus

My client offers a collaborative working environment with technically challenging projects, and the opportunity to influence layout practices company-wide.

Please note that this job requires 5 days on-site.

If you are a Senior IC Layout Design Engineer looking for a new opportunity in the Netherlands, feel free to get in touch for more details.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing and Engineering Services

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