Senior IC Design Engineer - Logic & ESD Lead

Nexperia; Nederland; Hybrid; EUR 65,000 - 95,000; Full time

Benefits offered by this job

Flexible working hours

Permanent contract

Bonus program

Career development

Travel allowance

Employee discounts

Job summary

Nexperia Nijmegen is seeking a Senior IC Design Engineer to join the Logic Solutions team. You will own the implementation of technical requirements for logic and switch family products, drive full-chip design, and ensure top-level layout fits for multiple packages.

You will collaborate across design, test and product quality engineering to meet datasheet specs and ESD requirements. The role requires a Master’s in EE, 3+ years in semiconductor circuit design, experience with CMOS/BCD processes,

Qualifications

• Master’s degree in electrical engineering.
• Minimum 3 years of semiconductor industry experience.
• Experience with CMOS/BCD technologies.
• Knowledge of ESD mechanisms and protection techniques.
• Experience with analog EDA tools and simulations.

Responsibilities

• Drive full-chip design and verification for logic and switch families.
• Set specifications and agree test limits with the team.
• Develop top-level layout and ensure package-fit across products.
• Collaborate with design, product quality, test and engineering teams.
• Implement ESD robust solutions and perform related characterization.

Skills

CMOS/BCD tech

Circuit design

EDA tools

ESD protection

Analytical skills

English communication

Team player

Independent work

Problem solving

Education

Master’s degree in Electrical Engineering

Tools

Synopsys

Cadence

Job description

Nexperia Nijmegen is seeking a Senior IC Design Engineer to join the Logic Solutions team. You will own the implementation of technical requirements for logic and switch family products, drive full-chip design, and ensure top-level layout fits for multiple packages.

You will collaborate across design, test and product quality engineering to meet datasheet specs and ESD requirements. The role requires a Master’s in EE, 3+ years in semiconductor circuit design, experience with CMOS/BCD processes,