Yield Development Engineer

Intel; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Intel Malaysia in Penang seeks a Yield Development Engineer to drive technology yield improvements across manufacturing. You will identify yield limiters, perform statistical analyses, and collaborate with process teams to optimize manufacturability.

The role emphasizes hands-on debugging, data consolidation, and development of measurement recipes. You will work with design, test, and process teams to implement improvements and advance yield modeling.

Qualifications

• Bachelor’s degree in electronic engineering or related field.
• 3+ years in semiconductor failure analysis or test engineering.
• Strong understanding of SCAN ATPG, fault models, and diagnostic methods.
• Proficiency in electrical fault isolation and layout analysis.
• Experience with data analysis and yield learning from silicon brings.

Responsibilities

• Identify yield limiters using statistical techniques and big data.
• Develop process development roadmaps to meet yield milestones.
• Consolidate and visualize data to extract actionable insights.
• Perform fault isolation and root-cause analysis.
• Collaborate with design, test, and process teams to improve manufacturability.
• Create measurement recipes and reinforce equipment capabilities.
• Lead new product introductions and design-technology co-optimization.
• Develop tools and algorithms for high-volume data analysis.
• Drive cross-functional collaboration to resolve yield, design, and process issues.

Skills

Statistical data analysis

Yield optimization

Failure analysis

ATE test data correlation

Cross-functional collaboration

Debug and fault isolation

Programming (Python/R)

DFT/ATP/SCAN familiarity

Machine learning basics

Education

Bachelor's in Electronic/Computer Engineering

Tools

Advantest

Teradyne

JMP/Python/R

Job description

Job Details

Job Description

As a Yield Development Engineer, you will play a critical role in advancing Intel's manufacturing capabilities by driving technology yield improvements. You will work hands‑on to identify yield limiters, conduct statistical analyses, and collaborate on process changes to optimize manufacturability. Your contributions will directly impact product quality, factory efficiency, and Intel's ability to deliver cutting‑edge technologies to market.

Business group The Intel Foundry team focuses on delivering high-performance solutions that empower customers across the globe. As part of this team, you will contribute to innovative process development and yield optimization efforts, supporting Intel's mission to lead in advanced semiconductor manufacturing. The group emphasizes collaboration and technical excellence to enable breakthrough innovations and industry‑leading outcomes.

Key Responsibilities

• Identify and analyze yield limiters using statistical techniques and big data methodologies.
• Develop and implement process development roadmaps to support technology yield milestones.
• Consolidate, interpret, and visualize diverse data sources to extract actionable insights for yield enhancement.
• Perform fault isolation and failure analysis to identify root causes of failures.
• Collaborate across design, test, and process teams to debug yield limiters and ensure manufacturability.
• Develop measurement recipes and harden equipment capabilities for advanced logic nodes.
• Execute new product introductions, design‑technology co‑optimization, and factory experiments to drive yield improvements.
• Create tools, algorithms, and systems to perform high-volume data analysis and advance yield modeling.
• Drive cross‑functional collaborations to resolve issues in yield, product design, and manufacturing processes.

Qualifications

• Bachelor's degree in electronic engineering, Computer Engineering or in a related field Technical Skills
• 3+ years of experience in semiconductor failure analysis or test engineering
• Strong understanding of Array architecture and failure mechanisms or hands‑on experience with SCAN ATPG methodology, including Scan chain diagnosis, ATPG pattern generation and debug, Fault models (stuck‑at, transition, path delay, bridging)
• Proficiency in fault isolation techniques, including Electrical fault isolation (EFI), circuit, and layout analysis
• Familiarity with failure signature analysis and yield learning Debug and Analysis
• Experience debugging logic and memory/array failures from silicon bring‑up through production
• Ability to correlate ATE test results with design and process data
• Experience with tester platforms (e.g., Advantest, Teradyne)
• Understanding of DFT (Design for Testability) concepts and implementation Preferred Qualifications
• Experience with embedded memory compilers and array redundancy analysis
• Familiarity with statistical data analysis tools (JMP, Python, R)
• Experience with nanometer process nodes (7nm, 5nm, 3nm, or below)
• Background in BIST (Built-In Self-Test) for memory and logic
• Exposure to machine learning-based fault classification or yield analysis
• Experience collaborating with design, process, and layout teams for root cause analysis

Soft Skills and Work Style

• Strong analytical and problem‑solving skills
• Ability to work in a fast‑paced, cross‑functional environment
• Excellent communication skills to present findings to engineering and management teams
• Self‑motivated with ability to manage multiple debug cases simultaneously
• Team player with experience working across design, process, and manufacturing organizations

Job Type

Experienced Hire

Shift

Shift 1 (Malaysia)

Primary Location

Malaysia, Penang

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on‑site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.