Staff Silicon Design Verification Engineer

AMD; Bayan Lepas; On-site; MYR 85,000 - 120,000; Full time

Job summary

A leading technology company in Penang is seeking a Staff Silicon Design Verification Engineer to focus on the verification of GPU IP features. The role involves collaborating with a diverse team of engineers and requires at least 5 years of experience in verification engineering and proficiency in ASIC level verification tools and methodologies. This position offers an opportunity to work within a dynamic team, with a strong emphasis on communication and problem-solving skills.

Qualifications

• 5+ years of work experience in verification engineering.
• Proficient in IP level ASIC verification.
• Proficient in debugging firmware and RTL code using simulation tools.
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language.

Responsibilities

• Collaborate with architects to understand features to be verified.
• Build test plan documentation for hardware and software interactions.
• Develop testbench components with UVM.
• Estimate time for new feature tests and test environment changes.
• Build verification tests and debug failures.

Skills

Communication skills

Analytical skills

Problem-solving skills

Team collaboration

Education

Bachelors or Masters degree in computer engineering/Electrical Engineering

Tools

Linux

Windows

UVM

Verilog

System Verilog

SVA

C

C++

Perl

Ruby

Makefile

Shell scripting

Job description

Staff Silicon Design Verification Engineer

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s GPU IP, resulting in no bugs in the final design.

THE PERSON:

You have a passion for modern, CPU or GPU architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Build testbench and develop the Testbench component with UVM
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, SVA, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Scripting language experience: Perl, Ruby, Makefile, shell preferred
• 5+ years of work experience in verification engineering

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

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